This paper introduces Embedded Deterministic Test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

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Pomeranz I(2018)Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside TestsACM Transactions on Design Automation of Electronic Systems10.1145/320140523:4(1-18)Online publication date: 29-May-2018
https://dl.acm.org/doi/10.1145/3201405
Pomeranz I(2018)Autonomous Multicycle Tests With Low Storage and Test Application Time OverheadsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277426937:9(1881-1892)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2774269
Pomeranz I(2017)LFSR-Based Generation of Multicycle TestsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258768736:3(503-507)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2587687
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Embedded Deterministic Test for Low-Cost Manufacturing Test
1. Applied computing

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ITC '02: Proceedings of the 2002 IEEE International Test Conference

October 2002

ISBN:0780375432

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IEEE Computer Society

United States

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Published: 07 October 2002

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Pomeranz I(2018)Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside TestsACM Transactions on Design Automation of Electronic Systems10.1145/320140523:4(1-18)Online publication date: 29-May-2018
https://dl.acm.org/doi/10.1145/3201405
Pomeranz I(2018)Autonomous Multicycle Tests With Low Storage and Test Application Time OverheadsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277426937:9(1881-1892)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2774269
Pomeranz I(2017)LFSR-Based Generation of Multicycle TestsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258768736:3(503-507)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2587687
Pomeranz I(2016)Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside TestsACM Transactions on Design Automation of Electronic Systems10.1145/291198322:1(1-22)Online publication date: 27-May-2016
https://dl.acm.org/doi/10.1145/2911983
Suresh CSinanoglu OOzev S(2016)Adapting to Varying Distribution of Unknown Response BitsACM Transactions on Design Automation of Electronic Systems10.1145/283548921:2(1-22)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2835489
Mehta UDasgupta KDevashrayee N(2010)Run-length-based test data compression techniquesVLSI Design10.1155/2010/6704762010(1-7)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/670476
Lee JTouba N(2010)Correlation-based rectangular encodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202588218:10(1483-1492)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025882
Pomeranz IReddy S(2010)On test generation with test vector improvementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204185329:3(502-506)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2041853
Czysz DMrugalski GMukherjee NRajski JTyszer J(2010)On compaction utilizing inter and intra-correlation of unknown statesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203555029:1(117-126)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TCAD.2009.2035550
Alves DBarros ESaraiva IRibas RPlett C(2009)A logic built-in self-test architecture that reuses manufacturing compressed scan test patternsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601923(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601923
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Low cost scan test by test correlation utilization

Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers

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