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10.5555/839296.843718guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
Article

A New Methodology for Improved Tester Utilization

Published: 30 October 2001 Publication History

Abstract

Typically the DFT features are decidedduring the design and remain fixed after thedesign is completed. This makes a devicetestable only on ATEs, which can satisfy thetest requirements for that chip. If such anATE is not available then the IC eithercannot be fully tested, or ATE resources arewasted when it is designed for lesscapabilities. This paper presents amethodology that builds on the testerretargetable pattern technology for testingICs on testers with different pin capabilitiesSuch a capability would be an essentialelement in reduced pin-count (multi-site)testing. The interfacing needs between theTest Automation World and the TesterEnvironment are also developed in thispaper.

References

[1]
M. Abromovici, M. A. Breuer, A. D. Friedman, "Digital Testing and Testable Systems", IEEE press 1995.
[2]
S. Narayanan S., M. A. Breuer, Recodigurable scan chains: A novel approach to reduce test application time, International Conference on Computer Aided Design (ICCAD), pp 710-715, 1993.
[3]
D. Mukherjee, M. Pedram, M. A. Breuer, Control strategies for chip based DFT/BIST hardware, International Test Conference, pp 893-902, 1994.
[4]
R. Kapur and T.W. Williams, "System and Method for Automatically Retargeting Test Vectors Between Different Testers," U.S. Patent Application, SNSY-A2000-036.
[5]
R. Kapur and T.W. Williams, "Tester Retargetable Patterns," International Test Conference, 2001.
[6]
R. Kapur, M. Lousberg, T. Taylor, B. Keller, P. Reuter and D. Kay, "CTL the language for describing Core Based Test," International Test Conference, 2001.

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Published In

cover image Guide Proceedings
ITC '01: Proceedings of the 2001 IEEE International Test Conference
October 2001
ISBN:0780371712

Publisher

IEEE Computer Society

United States

Publication History

Published: 30 October 2001

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