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Article

A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS

Authors:

Sybille Hellebrand,

Hans-Joachim WunderlichAuthors Info & Claims

ITC '00: Proceedings of the 2000 IEEE International Test Conference

Page 778

Published: 03 October 2000 Publication History

Abstract

In this paper a new scheme for deterministic andmixed mode scan-based BIST is presented. It relies on anew type of test pattern generator which resembles a programmable Johnson counter and is called foldingcounter. Both the theoretical background and practicalalgorithms are presented to characterize a set of deterministictest cubes by a reasonably small number of seeds for a folding counter. Combined with classical approachesfor test width compression and with pseudorandompattern generation these new techniques providean efficient and flexible solution for scan-based BIST.Experimental results show that the proposed schemeoutperforms previously published approaches based onthe reseeding of LFSRs or Johnson counters.

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Cited By

Moghaddam EMukherjee NRajski JSolecki JTyszer JZawada J(2019)Logic BIST With Capture-Per-Clock Hybrid Test PointsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283444138:6(1028-1041)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834441
Mrugalski GRajski JRybak LSolecki JTyszer J(2017)Star-EDTIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.259721436:4(683-693)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2597214
Lee JTouba N(2010)Correlation-based rectangular encodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202588218:10(1483-1492)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025882
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A mixed-mode BIST scheme based on folding compression
Abstract
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Information

Published In

cover image Guide Proceedings

ITC '00: Proceedings of the 2000 IEEE International Test Conference

October 2000

ISBN:0780365461

Copyright © Copyright (c) 2000 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 October 2000

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Cited By

Moghaddam EMukherjee NRajski JSolecki JTyszer JZawada J(2019)Logic BIST With Capture-Per-Clock Hybrid Test PointsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283444138:6(1028-1041)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834441
Mrugalski GRajski JRybak LSolecki JTyszer J(2017)Star-EDTIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.259721436:4(683-693)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2597214
Lee JTouba N(2010)Correlation-based rectangular encodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202588218:10(1483-1492)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025882
Wang ZChakrabarty KWang S(2009)Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202173128:8(1251-1264)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2021731
Wang ZFang HChakrabarty KBienek M(2009)Deviation-based LFSR reseeding for test-data compressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200916628:2(259-271)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009166
Li LWang ZChakrabarty K(2007)Scan-BIST based on cluster analysis and the encoding of repeating sequencesACM Transactions on Design Automation of Electronic Systems10.1145/1188275.118827912:1(1-21)Online publication date: 2-Feb-2007
https://dl.acm.org/doi/10.1145/1188275.1188279
Doi YKajihara SWen XLi LChakrabarty KTang T(2005)Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxationProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120744(59-64)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120744
Li LChakrabarty K(2005)Hybrid BIST Based on Repeating Sequences and Cluster AnalysisProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.177(1142-1147)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.177
Novák OZahrádka JPlíva Z(2005)COMPAS – compressed test pattern sequencer for scan based circuitsProceedings of the 5th European conference on Dependable Computing10.1007/11408901_30(403-414)Online publication date: 20-Apr-2005
https://dl.acm.org/doi/10.1007/11408901_30
Krishna CTouba N(2004)3-Stage Variable Length Continuous-Flow Scan Vector Decompression SchemeProceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987956Online publication date: 25-Apr-2004
https://dl.acm.org/doi/10.5555/987684.987956
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