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Article

Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks

Authors:

Niraj K. JhaAuthors Info & Claims

HPCA '03: Proceedings of the 9th International Symposium on High-Performance Computer Architecture

Page 91

Published: 08 February 2003 Publication History

Abstract

Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnectionnetworks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper, we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3X power savings (4.6X on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

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Cited By

Mirhosseini ASadrosadati MAghamohammadi FModarressi MSarbazi-Azad H(2019)BARANACM Transactions on Parallel Computing10.1145/32940495:3(1-29)Online publication date: 22-Jan-2019
https://dl.acm.org/doi/10.1145/3294049
Sarangi SGoel SSingh BHaddad HWainwright RChbeir R(2018)Energy efficient scheduling in IoT networksProceedings of the 33rd Annual ACM Symposium on Applied Computing10.1145/3167132.3167213(733-740)Online publication date: 9-Apr-2018
https://dl.acm.org/doi/10.1145/3167132.3167213
Kim GChoi HKim J(2018)TCEPProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00065(712-725)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00065
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Index Terms

Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. General and reference
  1. Cross-computing tools and techniques

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Published In

cover image Guide Proceedings

HPCA '03: Proceedings of the 9th International Symposium on High-Performance Computer Architecture

February 2003

ISBN:0769518710

Copyright © Copyright (c) 2003 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 08 February 2003

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Cited By

Mirhosseini ASadrosadati MAghamohammadi FModarressi MSarbazi-Azad H(2019)BARANACM Transactions on Parallel Computing10.1145/32940495:3(1-29)Online publication date: 22-Jan-2019
https://dl.acm.org/doi/10.1145/3294049
Sarangi SGoel SSingh BHaddad HWainwright RChbeir R(2018)Energy efficient scheduling in IoT networksProceedings of the 33rd Annual ACM Symposium on Applied Computing10.1145/3167132.3167213(733-740)Online publication date: 9-Apr-2018
https://dl.acm.org/doi/10.1145/3167132.3167213
Kim GChoi HKim J(2018)TCEPProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00065(712-725)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00065
Makaratzis AGiannoutakis KTzovaras D(2018)Energy modeling in cloud simulation frameworksFuture Generation Computer Systems10.1016/j.future.2017.06.01679:P2(715-725)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1016/j.future.2017.06.016
O’brien KPietri IReddy RLastovetsky ASakellariou R(2017)A Survey of Power and Energy Predictive Models in HPC Systems and ApplicationsACM Computing Surveys10.1145/307881150:3(1-38)Online publication date: 29-Jun-2017
https://dl.acm.org/doi/10.1145/3078811
Casu MGiaccone P(2017)Power-performance assessment of different DVFS control policies in NoCsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2017.06.004109:C(193-207)Online publication date: 1-Nov-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2017.06.004
Das SSadowski G(2016)Reconfigurable Links for Self-Timed On-Chip CommunicationProceedings of the 9th International Workshop on Network on Chip Architectures10.1145/2994133.2994141(15-20)Online publication date: 15-Oct-2016
https://dl.acm.org/doi/10.1145/2994133.2994141
Psarras ALee JMattheakis PNicopoulos CDimitrakopoulos GCoskun AMargala MBehjat LHan J(2016)A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-ProcessorsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903010(335-340)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903010
Li DWu J(2016)Energy-efficient contention-aware application mapping and scheduling on NoC-based MPSoCsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.04.00696:C(1-11)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1016/j.jpdc.2016.04.006
Bokhari HJavaid HShafique MHenkel JParameswaran SNebel WAtienza D(2015)Malleable NoCProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757101(1245-1248)Online publication date: 9-Mar-2015
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