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A verification technique for hardware designs

Authors:

Fumihiro Maruyama,

Takao Uehara,

Nobuaki Kawato,

Takao SaitoAuthors Info & Claims

DAC '82: Proceedings of the 19th Design Automation Conference

Pages 832 - 841

Published: 01 January 1982 Publication History

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Abstract

Most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. This paper discusses an analytic verification technique with examples of its application.

This technique employs backward symbolic simuation, or causality tracing, which is carried out from the negation of a proposition which should be verified. Analyticity this technique has, not only makes verification powerful but gives it another feature, design error diagnosis.

References

[1]

J.R. Duley and D.L. Dietmeyer: "A Digital System Design Language (DDL)," IEEE Trans. Computers Vol. C-17, pp. 850-861 (1968).

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[2]

J.R. Duley and D.L. Dietmeyer: "Translation of a DDL Digital System Specification to Boolean Equation," IEEE Trans. Computers, Vol. C-18, pp. 305-313 (1969).

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[3]

N. Kawato, T. Saito, F. Maruyama and T. Uehara: "Design and Verification of Large Scale Computer by Using DDL," Proc. 16th Design Automation Conference, pp. 360-366, June (1979).

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[4]

Stanford verification group: "Stanford Pascal Verifier User Manual," Comp. Sci. Dept., Reprt No. STAN-CS-79-731, Stanford Univ., March (1979).

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T.J. Wagner: "Hardware Verification," Ph.D. dissertation, Comp. Sci. Dept., Report No. STAN-CS-77-632, Stanford Univ., Sept. (1977).

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Odawara GTomita MOkuzawa OOhta TZhuang ZThomas D(1986)A logic verifier based on Boolean comparisonProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318046(208-214)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318046
Wojcik AKljaich JSrinivas NLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)A formal design verification system based on an automated reasoning systemProceedings of the 21st Design Automation Conference10.5555/800033.800867(641-647)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800867
Wojcik ARadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)Formal design verification of digital systemsProceedings of the 20th Design Automation Conference10.5555/800032.800668(228-234)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800668

Index Terms

A verification technique for hardware designs
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
  2. Hardware validation
    1. Functional verification

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DAC '82: Proceedings of the 19th Design Automation Conference

January 1982

919 pages

ISBN:0897910206

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IEEE Press

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Published: 01 January 1982

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Odawara GTomita MOkuzawa OOhta TZhuang ZThomas D(1986)A logic verifier based on Boolean comparisonProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318046(208-214)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318046
Wojcik AKljaich JSrinivas NLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)A formal design verification system based on an automated reasoning systemProceedings of the 21st Design Automation Conference10.5555/800033.800867(641-647)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800867
Wojcik ARadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)Formal design verification of digital systemsProceedings of the 20th Design Automation Conference10.5555/800032.800668(228-234)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800668

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Abstract

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Recommendations

Industrial Strength Formal Verification Techniques for Hardware Designs

Verification of Hardware Designs: A Case Study

Formal verification in hardware design: a survey

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