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Functional design verification by multi-level simulation

Authors:

Kit Tham,

Rob Willoner,

David WimpAuthors Info & Claims

DAC '84: Proceedings of the 21st Design Automation Conference

Pages 473 - 478

Published: 25 June 1984 Publication History

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Abstract

This paper introduces Intel's functional CAD design environment and methodology. The generation of an accurate behavioral model for use in systems design validation and for comparisons with lower-level components is described. The need for both an RTL and a schematics simulator in Intel's hierarchical design methodology is explained. Finally, the paper shows how these two simulators have been linked together in two ways for two different purposes: for RTL-schematics verification, and for very large logic simulation runs.

References

[1]

Wilcox, C. R., et al, "MAINSAIL Language Manual", Xidak, Inc., August 1979

Google Scholar

[2]

Teel, B. and Wilde, D., "A Logic Minimizer For VLSI PLA Design", Nineteenth Design Automation Conference Proceedings, ACM, IEEE, 1982, pp 156 - 162

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Google Scholar

[3]

Bryant, R., "A Switch-Level Model and Simulator for MOS Digital Systems", Technical Report 5065, Department of Computer Science, California Institute of Technology, January 1983

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Google Scholar

[4]

Bryant, R., Schuster, M. and Whiting, D., "MOSSIM II: A Switch-Level Simulator for MOS LSI. Users' Manual", Department of Computer Science, California Institute of Technology, October 1983

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Cited By

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Maurer P(1990)Dynamic Functional Testing for VLSI CircuitsIEEE Design & Test10.1109/54.649567:6(42-49)Online publication date: 1-Nov-1990
https://dl.acm.org/doi/10.1109/54.64956
Wang ZMaurer PThomas D(1989)Scheduling high-level blocks for functional simulationProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74398(87-90)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74398
Lathrop RKirk ROfek HO'Neill L(1985)An extensible object-oriented mixed-mod functional simulation systemProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317956(630-636)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317956
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Index Terms

Functional design verification by multi-level simulation
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Published In

DAC '84: Proceedings of the 21st Design Automation Conference

June 1984

715 pages

ISBN:0818605421

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IEEE Press

Publication History

Published: 25 June 1984

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DAC '84 Paper Acceptance Rate 116 of 290 submissions, 40%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Maurer P(1990)Dynamic Functional Testing for VLSI CircuitsIEEE Design & Test10.1109/54.649567:6(42-49)Online publication date: 1-Nov-1990
https://dl.acm.org/doi/10.1109/54.64956
Wang ZMaurer PThomas D(1989)Scheduling high-level blocks for functional simulationProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74398(87-90)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74398
Lathrop RKirk ROfek HO'Neill L(1985)An extensible object-oriented mixed-mod functional simulation systemProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317956(630-636)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317956
Mar JWei YLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)Performance verification of circuitsProceedings of the 21st Design Automation Conference10.5555/800033.800842(479-483)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800842

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Recommendations

Parallel multi-level simulation with a conservative approach

Runtime Abstraction-Level Conversion of Discrete-Event Wafer-fabrication Models for Simulation Acceleration

Functional abstraction in switch-level simulation