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Functional modelling for logic simulation

Published: 29 June 1981 Publication History

Abstract

As digital integrated circuits become more complex, Computer Aided Design (CAD) must support more hierarchical design methods. Top-down design is supported in logic simulators by the inclusion of functional models. The SAndia LOGic Simulator (SALOGS) has functional modelling capability but until now only as FORTRAN subroutines. The new Structural Interface to the SALOGS Language (SISL) allows the design engineer access to the functional modelling capabilities without requiring the associated programming skills. The SISL syntax is described and a sample functional model library is presented.

References

[1]
Preas, B. T. and Gwyn, C. W., "Architecture for Contemporary Computer Aids to Generate IC Mask Layouts," Conf. Record 11th Asilomar, Conf. on Circuits, Systems and Computers, pp 353-361 (November 1977).
[2]
Preas, B. T. and Gwyn, C. W., "Methods for Hierarchical Automatic Layout of Custom LSI Circuit Masks," Proc. 15th Design Automation Conf., pp 206-212 (June 1978).
[3]
Raeth, P. G., A Functional Level Preprocessor for Computer-Aided Digital Design, Unpublished thesis, Air Force Institute of Technology (December 1980).
[4]
Acken, J. M., Stauffer, J. D., "Part 1: Logic Circuit Simulation," IEEE Circuits and Systems Magazine, Vol. No. 1, pp 9-13 (March 1979).
[5]
Barbacci, M., Barnes, G., Cattell, R., Siewiorek, D., "The Symbolic Manipulation of Computer Descriptions: The ISPS Computer Description Language," Department of Computer Science, Carnegie-Mellon University, Pittsburgh, Pa. (March 1978).
[6]
Parker, A., Thomas, D., Siewiorek, D., Barbacci, M., Hafer, L., Leive, G., Kim, J., "The CMU Design Automation System: An Example of Automated Path Design," Proc. 16th Design Automation Conference, pp 73-79 (June 1979).
[7]
vanCleemput, W. M., "An Hierarchical Language for the Structural Description of Digital Systems," Proc. 14th Design Automation Conference, pp 377-385 (June 1977).
[8]
Acken, J. M., Goldstein, L. H., "Delay Modelling in Logic Simulation," Proc. of IEEE International Conf. on Circuits and Computers, pp 944-947 (October 1980).

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cover image ACM Conferences
DAC '81: Proceedings of the 18th Design Automation Conference
June 1981
899 pages

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IEEE Press

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Published: 29 June 1981

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