Modifying User-Defined Logic for Test Access to Embedded Cores

Testing embedded cores is a challenge becauseaccess to core I/Os is limited. The user-defined logic(UDL) surrounding the core may restrict the set of testvectors that can be applied to the core. Consequently,some of the core test vectors specified by the coresupplier may not be contained in the output space of theUDL that drives the core and hence cannot be justified atthe core inputs. Conventional solutions to this probleminvolve placing multiplexers or boundary scan elementsat the inputs of the core to provide test access. This canbe very costly in terms of area and performance. Thispaper presents a new approach for providing test accessto an embedded core. A procedure is described forinserting control points in the UDL to modify its outputspace so that it contains the specified core test vectors.The flexibility in selecting the location of the controlpoints is used to avoid performance degradation bykeeping test logic off the critical timing paths.Experimental results are shown comparing the controlpoint insertion procedure with other approaches.