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10.5555/792770.793695guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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System Overview of the SGI Origin 200/2OOO Product Line

Published: 23 February 1997 Publication History

Abstract

The SGI Origin 200/2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor, designed and manufactured by Silicon Graphics Inc. (SGI). The Origin system was designed from the ground up as a multiprocessor that was capable of scaling to both small and large processor counts without any cost, bandwidth or latency cliffs. The Origin system consists of up to 512 nodes interconnected by a highly scalable Craylink network. Each node consists of one or two R10000 processors and up to 4 GBytes of coherent memory. Each node also connects to the scalable XIO I/O subsystem. This paper discusses the motivation for building the Origin 200/2000 and describes its architecture and implementation.

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  • (2011)Hamiltonian cycle within extended OTIS-cube topologyProceedings of the 10th WSEAS international conference on communications, electrical & computer engineering, and 9th WSEAS international conference on Applied electromagnetics, wireless and optical communications10.5555/1989676.1989699(118-122)Online publication date: 24-Mar-2011
  • (2004)Using Hardware Counters to Automatically Improve Memory PerformanceProceedings of the 2004 ACM/IEEE conference on Supercomputing10.1109/SC.2004.64Online publication date: 6-Nov-2004
  • (2003)Server I/O networks past, present, and futureProceedings of the ACM SIGCOMM workshop on Network-I/O convergence: experience, lessons, implications10.1145/944747.944749(163-178)Online publication date: 25-Aug-2003
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Information & Contributors

Information

Published In

cover image Guide Proceedings
COMPCON '97: Proceedings of the 42nd IEEE International Computer Conference
February 1997
ISBN:0818678046

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IEEE Computer Society

United States

Publication History

Published: 23 February 1997

Author Tags

  1. 4 GB
  2. R10000 processors
  3. SGI Origin 200/2000
  4. Silicon Graphics Inc.
  5. bandwidth
  6. cache-coherent nonuniform memory access multiprocessor
  7. ccNUMA multiprocessor
  8. coherent memory
  9. cost
  10. implementation
  11. interconnected nodes
  12. latency
  13. multiprocessing systems
  14. processor number
  15. scalable Craylink network
  16. scalable XIO I/O subsystem
  17. system architecture

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View all
  • (2011)Hamiltonian cycle within extended OTIS-cube topologyProceedings of the 10th WSEAS international conference on communications, electrical & computer engineering, and 9th WSEAS international conference on Applied electromagnetics, wireless and optical communications10.5555/1989676.1989699(118-122)Online publication date: 24-Mar-2011
  • (2004)Using Hardware Counters to Automatically Improve Memory PerformanceProceedings of the 2004 ACM/IEEE conference on Supercomputing10.1109/SC.2004.64Online publication date: 6-Nov-2004
  • (2003)Server I/O networks past, present, and futureProceedings of the ACM SIGCOMM workshop on Network-I/O convergence: experience, lessons, implications10.1145/944747.944749(163-178)Online publication date: 25-Aug-2003
  • (2000)The Formal Design of 1M-gate ASICsFormal Methods in System Design10.1023/A:100877330810816:1(7-22)Online publication date: 1-Jan-2000
  • (1997)Scalability in computing for today and tomorrowProceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)10.5555/786452.786706Online publication date: 15-Sep-1997

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