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A CMOS Low Voltage, High Gain Op-Amp

Authors:

Guo-Neng Lu,

Gerard SouAuthors Info & Claims

EDTC '97: Proceedings of the 1997 European conference on Design and Test

Page 51

Published: 17 March 1997 Publication History

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Abstract

A CMOS, self biasing, single supply op-amp is presented. It is designed with regulated cascode transistors for gain enhancement and a common mode feedback technique for bias stabilisation of complementary regulated cascodes. It enables supply voltage lowering to about 2|Vt|+2|Vds,sat| with the maintain of high gain operation. At Vdd=1.8 V, the measured DC gain of the op-amp is 115 dB, whit a unity gain frequency of 8.6 MHz for a capacitive load of 20 pF.

References

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{2} Yang H. C., and Allstot D. J.: "An active-feedback cascade current source", IEEE Trans. Circuits Syst., 1990, 37, (5), pp. 644-646.

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{3} Bult K., and Geelen G.: "A fast-settling CMOS op-amp for SC circuits with 90-dB DC gain", IEEE J. Solid-State Circuits, 1990, SC-25, (6), pp. 1379-1384.

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A CMOS Low Voltage, High Gain Op-Amp
1. Hardware

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Published In

EDTC '97: Proceedings of the 1997 European conference on Design and Test

March 1997

596 pages

ISBN:0818677864

Publisher

IEEE Computer Society

United States

Publication History

Published: 17 March 1997

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Conference

EDTC96

Sponsor:

SIGDA

EDTC96: European Design and Test Conference

March 17 - 20, 1997

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