An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS)

This paper reports the design of a T est P attern Generator (TPG) for V LSI circuits. The on-chip TPG is so designed that it generates test patterns while avoiding generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-...

This work reports the design of a fool proof on-chip test pattern generator (TPG) for very large scale integration circuits. The TPG is designed to generate pseudorandom test patterns without a given prohibited pattern set (PPS). It ensures desired ...

This paper reports an efficient BIST solution for VLSI circuits. The solution is based on an on-chip Pseudo-Random Pattern Generator ( PRPG ) for the CUT s (Circuit Under Test) of a VLSI chip that may be accessed through a full or partial scan ...