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Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST

Published: 21 October 1995 Publication History

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  • (2009)Operating system scheduling for efficient online self-test in robust systemsProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687436(201-208)Online publication date: 2-Nov-2009
  • (2006)Improving linear test data compressionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641714:11(1227-1237)Online publication date: 1-Nov-2006
  • (2004)Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing CompactorJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000009317.31947.c820:1(109-122)Online publication date: 1-Feb-2004
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  1. Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST

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    Published In

    cover image Guide Proceedings
    Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
    October 1995
    964 pages
    ISBN:0780329929

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 21 October 1995

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    • (2009)Operating system scheduling for efficient online self-test in robust systemsProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687436(201-208)Online publication date: 2-Nov-2009
    • (2006)Improving linear test data compressionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641714:11(1227-1237)Online publication date: 1-Nov-2006
    • (2004)Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing CompactorJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000009317.31947.c820:1(109-122)Online publication date: 1-Feb-2004
    • (2003)A BIST Pattern Generator Design for Near-Perfect Fault CoverageIEEE Transactions on Computers10.1109/TC.2003.125285152:12(1543-1558)Online publication date: 1-Dec-2003
    • (2003)A Ring Architecture Strategy for BIST Test Pattern GenerationJournal of Electronic Testing: Theory and Applications10.1023/A:102378872754219:3(223-231)Online publication date: 1-Jun-2003
    • (2002)On-the-Fly ReseedingJournal of Electronic Testing: Theory and Applications10.1023/A:101503932316818:3(315-332)Online publication date: 1-Jun-2002
    • (2001)On Using Twisted-Ring Counters for Test Set Embedding in BISTJournal of Electronic Testing: Theory and Applications10.1023/A:101287270612317:6(529-542)Online publication date: 1-Dec-2001
    • (2000)On Using Deterministic Test Sets in BISTProceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)10.5555/850960.854344Online publication date: 3-Jul-2000
    • (2000)Efficient Test Mode Selection & Insertion for RTL-BISTProceedings of the 2000 IEEE International Test Conference10.5555/839295.843634Online publication date: 3-Oct-2000
    • (2000)Test of future system-on-chipsProceedings of the 2000 IEEE/ACM international conference on Computer-aided design10.5555/602902.602991(392-399)Online publication date: 5-Nov-2000
    • Show More Cited By

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