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Message Dispatch on Pipelined Processors

Published: 07 August 1995 Publication History

Abstract

Object-oriented systems must implement message dispatch efficiently in order not to penalize the object-oriented programming style. We characterize the performance of most previously published dispatch techniques for both statically- and dynamically-typed languages with both single and multiple inheritance. Hardware organization (in particular, branch latency and superscalar instruction issue) significantly impacts dispatch performance. For example, inline caching may outperform C++-style "vtables" on deeply pipelined processors even though it executes more instructions per dispatch.We also show that adding support for dynamic typing or multiple inheritance does not significantly impact dispatch speed for most techniques, especially on superscalar machines. Instruction space overhead (calling sequences) can exceed the space cost of data structures (dispatch tables), so that minimal table size may not imply minimal run-time space usage.

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cover image Guide Proceedings
ECOOP '95: Proceedings of the 9th European Conference on Object-Oriented Programming
August 1995
470 pages
ISBN:3540601600

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 07 August 1995

Author Tags

  1. computer architecture
  2. implementation
  3. message dispatch
  4. performance

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