More Web Proxy on the site http://driver.im/

Article

Hardware Versus Software Implementation of COMA

Authors:

Alain GefflautAuthors Info & Claims

ICPP '97: Proceedings of the international Conference on Parallel Processing

Pages 248 - 256

Published: 11 August 1997 Publication History

Abstract

Traditionally, cache coherence in multiprocessors has been maintained in hardware. However, the cost-effectiveness of hardwired protocols is questionable. Virtual Shared Memory systems have highlighted the many advantages of software-implemented protocols, albeit at a performance price. The performance gap is narrowed by hybrid systems with the addition of hardware support for fine-grain sharing. We have developed a software protocol for a COMA (Cache-Only Memory Architecture). We call the system SC-COMA for Software-Controlled COMA, to emphasize that the protocol engine is emulated by software executed on the main processor. Contrary to user-level protocols, the software handling coherence events in SC-COMA runs in sub-kernel mode, transparently providing the same services to applications as a hardware counterpart. The software emulation layer has been written and we compare SC-COMA to an idealized hardware COMA through detailed simulations. Our results show that SC-COMA is competitive. On systems with 32 processors, it achieves a slowdown of 11-56% with respect to its hardware counterpart, across a range of applications and memory pressures. SC-COMA scales well, up to 32 nodes. A study on the impact of faster processors on SC-COMA's relative performance indicates a consistent improvement, but with a limitation due to the loosely-integrated design. We conclude that SC-COMA is a viable solution to easily transform networks of workstations into powerful multiprocessors.

References

[1]

M. Björklund, F. Dahlgren, P. Stenström. Using Hints to Reduce the Read Miss Penalty for Flat COMA Protocols. Proc of the 28th Hawaii International Conference on System Sciences, pp. 242-251, 1995.

Digital Library

[2]

W.J. Bolosky. Software Coherence in Multiprocessor Memory Systems. PhD. Thesis. University of Rochester, 1993.

Digital Library

[3]

H. Burkhardt III et al. Overview of the KSR-1 Computer System. Technical Report KSR-TR-9202001, Kendall Square Research, Feb. 1992.

[4]

D. Chaiken, A. Agarwal. Software Extended Coherent Shared Memory: Performance and Cost. Proc. of the 21st Int. Symposium on Computer Architecture, pp. 314-324, May 1994.

Digital Library

[5]

Derek Chiou et al. StarT-NG: Delivering Seamless Parallel Computing. Euro-Par'95, Aug. 1995.

Digital Library

[6]

M. Dubois, J. Skeppstedt, P. Stenström. Essential Misses and Data Traffic in Coherence Protocols. Journal of Parallel and Distributed Computing, Vol. 29, No.2, pp. 108-125, Sep. 1995.

Digital Library

[7]

S. Dwarkadas, P. Keheler, A.L. Cox, W. Zwaenepoel. Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology. Proc. of the 20th Annual Int. Symp. on Computer Architecture, pp. 144-155, 1993.

Digital Library

[8]

H. Grahn, P. Stenström. Efficient Strategies for Software-Only Directory Protocols in Shared-Memory Multiprocessors. Proc. of the 22nd Annual International Symposium on Computer Architecture. Santa Margherita, Italy, Jun. 1995.

Digital Library

[9]

E. Hagersten, A. Landin, S. Haridi. DDM-A Cache-Only Memory Architecture. IEEE Computer, Vol. 25, No.9, pp. 44-54, Sep. 1992.

Digital Library

[10]

M. Heinrich et al. The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor. Proc. of the Sixth Int. Conf. on Arch. Support for Programming Languages and Operating Systems, pp 274-285, 1994.

Digital Library

[11]

C. Holt, M. Heinrich, J.P. Singh, E. Rothberg, J. Hennessy. The Effects of Latency, Occupancy, and Bandwidth in Distributed Shared Memory Multiprocessors. Technical Report CSL-TR-95-660, Computer Systems Laboratory. Stanford University, Jan. 1995.

Digital Library

[12]

M. Horowitz, M. Martonosi, T.C. Mowry, M.D. Smith. Informing Memory Operations: Providing Memory Performance Feedback in Modem Processors. Proceedings of the 23rd Annual Symposium on Computer Architecture, pages 260-270, 1996.

Digital Library

[13]

T. Joe. COMA-F: a Non-Hierarchical Cache Only Memory Architecture. PhD. Thesis, Stanford University, Mar. 1995.

Digital Library

[14]

J. Kubiatowicz, D. Chaiken, A. Agarwal. Closing the Window of Vulnerability in Multiphase Memory Transactions. Proc. of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems. ACM Sigplan Notices, Volume 27, Number 9, Sep. 1992.

Digital Library

[15]

J. Kuskin et al. The Stanford FLASH Multiprocessor. Proc. of the 21st Annual International Symposium on Computer Architecture. Apr. 1994.

Digital Library

[16]

D.E. Lenoski et al. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. Proc. of the 17th Annual Int. Symp. on Computer Architecture, pp 148-159, 1990

Digital Library

[17]

K. Li. IVY: A Shared Virtual Memory System for Parallel Computing. Proc. of the Int. Parallel Processing Conference pp. 94-101, 1988.

[18]

A. Moga, A. Gefflaut, M. Dubois. Hardware versus Software Implementation of COMA. Technical Report CENG 97-03. University of Southern California. Jan. 1997.

[19]

A. Nowatzyk et al. The S3.mp Scalable Shared Memory Multiprocessor. Proc. of the Int. Parallel Processing Conference, pp. I-1-I-10, 1995.

[20]

S.K. Reinhardt, J.R. Larus, D.A. Wood. Tempest and Typhoon: User-level Shared Memory. Proc. of the 21st Annual International Symposium on Computer Architecture, pages 325- 337, Apr. 1994.

Digital Library

[21]

S.K. Reinhardt, R.W. Pfile, D.A. Wood. Decoupled Hardware Support for Distributed Shared Memory. Proc. of the 23rd International Symposium on Computer Architecture, May 1996.

Digital Library

[22]

A. Saulsbury, T. Wilkinson, J. Carter and A. Landin. An Argument for Simple COMA. Proc. of the 1st Symposium on High-Peiformance Computer Architecture, pages 276-285, Raleigh, Jan. 1995.

Digital Library

[23]

A. Saulsbury, F. Pong, A. Nowatzyk. Missing the Memory Wall: The Case for Processor/Memory Integration. Proc. of the 23rd Annual Int. Symp. on Computer Architecture, 1996.

Digital Library

[24]

D.J. Scales, K. Gharachorloo, C.A. Thekkath. Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory. Proceedings of the 3rd International Symposium on High-Peiformance Computer Architecture, 1997.

Digital Library

[25]

I. Schoinas, B. Falsafi, A.R. Lebeck, S.K. Reinhardt, J.R. Larus and D.A. Wood. Fine-grain Access Control for Distributed Shared Memory. Proc. of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems. Oct. 1994.

Digital Library

[26]

P. Stenström, T. Joe, A. Gupta. Comparative Performance Evaluation of Cache-Coherent NUMA and COMA architectures. Proc. of the 19th Annual Symposium on Computer Architecture, pages 80-91, May 1992.

Digital Library

[27]

J. Torrellas, D. Padua. The Illinois Aggressive COMA Multiprocessor Project (I-ACOMA). 6th Symposium on the Frontiers of Massively Parallel Computing, Oct. 1996.

Digital Library

[28]

S. Woo et al. The SPLASH-2 Programs: Characterization and Methodological Considerations. Proc. of the 23rd Int. Symp. on Computer Architecture, pp. 24-36, 1995.

Digital Library

Cited By

Qiu XDubois M(2005)Moving Address Translation Closer to Memory in Distributed Shared-Memory MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2005.8416:7(612-623)Online publication date: 1-Jul-2005
https://dl.acm.org/doi/10.1109/TPDS.2005.84
Qiu XDubois M(2004)Tolerating Late Memory Traps in Dynamically Scheduled ProcessorsIEEE Transactions on Computers10.1109/TC.2004.1853:6(732-743)Online publication date: 1-Jun-2004
https://dl.acm.org/doi/10.1109/TC.2004.18
Qiu XDubois M(1999)Tolerating late memory traps in ILP processorsACM SIGARCH Computer Architecture News10.1145/307338.30098627:2(76-87)Online publication date: 1-May-1999
https://dl.acm.org/doi/10.1145/307338.300986
Show More Cited By

Hardware Versus Software Implementation of COMA
1. Computer systems organization
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

Recommendations

A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols
Special issue on cache memory and related problems

Scalable cache coherence protocols have become the key technology for creating moderate to large-scale shared-memory multiprocessors. Although the performance of such multiprocessors depends critically on the performance of the cache coherence protocol, ...
A comparative evaluation of hybrid distributed shared-memory systems

Distributed Shared-Memory (DSM) systems are shared-memory multiprocessor architectures in which each processor node contains a partition of the shared memory. In hybrid DSM systems coherence among caches is maintained by a software-implemented coherence ...
Performance of One's Complement Caches

On-chip caches to reduce average memory access latency are commonplace in today's commercial microprocessors. These on-chip caches generally have low associativity and small cache sizes. Cache line conflicts are the main source of cache misses, which ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image Guide Proceedings

ICPP '97: Proceedings of the international Conference on Parallel Processing

August 1997

334 pages

ISBN:081868108X

Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 11 August 1997

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 31 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Qiu XDubois M(2005)Moving Address Translation Closer to Memory in Distributed Shared-Memory MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2005.8416:7(612-623)Online publication date: 1-Jul-2005
https://dl.acm.org/doi/10.1109/TPDS.2005.84
Qiu XDubois M(2004)Tolerating Late Memory Traps in Dynamically Scheduled ProcessorsIEEE Transactions on Computers10.1109/TC.2004.1853:6(732-743)Online publication date: 1-Jun-2004
https://dl.acm.org/doi/10.1109/TC.2004.18
Qiu XDubois M(1999)Tolerating late memory traps in ILP processorsACM SIGARCH Computer Architecture News10.1145/307338.30098627:2(76-87)Online publication date: 1-May-1999
https://dl.acm.org/doi/10.1145/307338.300986
Qiu XDubois MGottlieb ADally W(1999)Tolerating late memory traps in ILP processorsProceedings of the 26th annual international symposium on Computer architecture10.1145/300979.300986(76-87)Online publication date: 2-May-1999
https://dl.acm.org/doi/10.1145/300979.300986
Qiu XDubois M(1998)Options for dynamic address translation in COMAsACM SIGARCH Computer Architecture News10.1145/279361.27939026:3(214-225)Online publication date: 16-Apr-1998
https://dl.acm.org/doi/10.1145/279361.279390
Qiu XDubois MValero MSohi G(1998)Options for dynamic address translation in COMAsProceedings of the 25th annual international symposium on Computer architecture10.1145/279358.279390(214-225)Online publication date: 16-Apr-1998
https://dl.acm.org/doi/10.1145/279358.279390

View Options

View options

Media

Figures

Other

Tables

View Table of Contents