Article

A 13.3ns double-precision floating-point ALU and multiplier

Authors:

H. SawamotoAuthors Info & Claims

ICCD '95: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors

Page 466

Published: 02 October 1995 Publication History

Publisher Site

Abstract

One-bit pre-shifting before alignment shift, normalization with anticipated leading '1' bit and pre-rounding techniques have been developed for a floating-point arithmetic logic unit (ALU). In addition, carry select addition and pre-rounding techniques have been developed for a floating-point multiplier. A noise tolerant precharge (NTP) circuit was designed and applied to the ALU and multiplier. These techniques reduced the delay time of the critical path by 24%. Each unit was fabricated in 0.3 /spl mu/m 2.5 V four-layer-metal CMOS technology and achieved a two-cycle latency at 150 MHz.

Cited By

View all

Harris DBreed GErler MDiaz DStan MGarrett DNakajima K(2003)Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logicProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764876(261-264)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764876
(2000)Skewed CMOSProceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors10.5555/557517.846819Online publication date: 17-Sep-2000
https://dl.acm.org/doi/10.5555/557517.846819

Recommendations

Array-of-arrays architecture for parallel floating point multiplication
ARVLSI '95: Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

A Abstract: This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the ...
A floating point radix 2 shared division/square root chip
ICCD '95: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors

This paper presents the architecture and implementation of a full-custom 1.2 micron CMOS VLSI chip that executes a shared division/square root algorithm operating on mantissas (23-b in length) of single precision IEEE 754 std. floating point numbers. ...
Interlock Collapsing ALU's

A device capable of executing interlocked fixed point arithmetic logic unit (ALU) instructions in parallel with other instructions causing the execution interlock is presented. The device incorporates the design of a 3-1 ALU and can execute two's ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICCD '95: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors

October 1995

448 pages

ISBN:0818671653

Publisher

IEEE Computer Society

United States

Publication History

Published: 02 October 1995

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 19 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Harris DBreed GErler MDiaz DStan MGarrett DNakajima K(2003)Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logicProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764876(261-264)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764876
(2000)Skewed CMOSProceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors10.5555/557517.846819Online publication date: 17-Sep-2000
https://dl.acm.org/doi/10.5555/557517.846819

Abstract

Cited By

Recommendations

Array-of-arrays architecture for parallel floating point multiplication

A floating point radix 2 shared division/square root chip

Interlock Collapsing ALU's

Comments

Information

Published In

Publisher

Publication History

Author Tags

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations