Article

Internal architecture of Alpha 21164 microprocessor

Authors:

P. Bannon,

J. KellerAuthors Info & Claims

COMPCON '95: Proceedings of the 40th IEEE Computer Society International Conference

Page 79

Published: 05 March 1995 Publication History

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Abstract

The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world's fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.

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King STucek JCozzie AGrier CJiang WZhou Y(2008)Designing and implementing malicious hardwareProceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats10.5555/1387709.1387714(1-8)Online publication date: 15-Apr-2008
https://dl.acm.org/doi/10.5555/1387709.1387714
Rudd KFlynn M(1997)Instruction-level parallel processors-dynamic and static scheduling tradeoffsProceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis10.5555/523978.826105Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/523978.826105
Oberman SFlynn M(1997)Division Algorithms and ImplementationsIEEE Transactions on Computers10.1109/12.60927446:8(833-854)Online publication date: 1-Aug-1997
https://dl.acm.org/doi/10.1109/12.609274
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Internal architecture of Alpha 21164 microprocessor

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COMPCON '95: Proceedings of the 40th IEEE Computer Society International Conference

March 1995

ISBN:0818670290

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IEEE Computer Society

United States

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Published: 05 March 1995

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King STucek JCozzie AGrier CJiang WZhou Y(2008)Designing and implementing malicious hardwareProceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats10.5555/1387709.1387714(1-8)Online publication date: 15-Apr-2008
https://dl.acm.org/doi/10.5555/1387709.1387714
Rudd KFlynn M(1997)Instruction-level parallel processors-dynamic and static scheduling tradeoffsProceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis10.5555/523978.826105Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/523978.826105
Oberman SFlynn M(1997)Division Algorithms and ImplementationsIEEE Transactions on Computers10.1109/12.60927446:8(833-854)Online publication date: 1-Aug-1997
https://dl.acm.org/doi/10.1109/12.609274
Cvetanovic ZBhandarkar D(1996)Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC WorkloadsProceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture10.5555/525424.822649Online publication date: 3-Feb-1996
https://dl.acm.org/doi/10.5555/525424.822649
Peir JHsu WYoung HOng S(1996)Improving cache performance with balanced tag and data pathsACM SIGPLAN Notices10.1145/248209.23720231:9(268-278)Online publication date: 1-Sep-1996
https://dl.acm.org/doi/10.1145/248209.237202
Lipasti MWilkerson CShen J(1996)Value locality and load value predictionACM SIGPLAN Notices10.1145/248209.23717331:9(138-147)Online publication date: 1-Sep-1996
https://dl.acm.org/doi/10.1145/248209.237173
Peir JHsu WYoung HOng S(1996)Improving cache performance with balanced tag and data pathsACM SIGOPS Operating Systems Review10.1145/248208.23720230:5(268-278)Online publication date: 1-Sep-1996
https://dl.acm.org/doi/10.1145/248208.237202
Lipasti MWilkerson CShen J(1996)Value locality and load value predictionACM SIGOPS Operating Systems Review10.1145/248208.23717330:5(138-147)Online publication date: 1-Sep-1996
https://dl.acm.org/doi/10.1145/248208.237173
Wasserman HYew P(1996)Benchmark tests on the Digital Equipment Corporation Alpha AXP 21164-based AlphaServer 8400, including a comparison of optimized vector and superscalar processingProceedings of the 10th international conference on Supercomputing10.1145/237578.237632(333-340)Online publication date: 1-Jan-1996
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Peir JHsu WYoung HOng SDally BEggets S(1996)Improving cache performance with balanced tag and data pathsProceedings of the seventh international conference on Architectural support for programming languages and operating systems10.1145/237090.237202(268-278)Online publication date: 1-Oct-1996
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Superscalar Instruction Execution in the 21164 Alpha Microprocessor

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