Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors

The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. Such a study is interesting as the dynamic instruction ordering and register renaming support mechanisms in out-of-order issue processors are similar in spirit to what the complex register allocation and instruction scheduling techniques do at compile-time.We evaluated four existing techniques, namely Postpass Scheduling, Prepass Scheduling, Parallel Interference Graph, and Integrated Prepass Scheduling methods. Our initial experimental results reveal that for o-o-o issue processors the focus should be on reducing the register pressure/spill code than exposing the parallelism at compiling time.