Article

Silicon debug of a co-processor array for video applications

Authors:

B. Vermeulen,

G. J. van RootselaarAuthors Info & Claims

HLDVT '00: Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)

Page 47

Published: 08 November 2000 Publication History

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Abstract

For today's multi-million transistor ICs, existing design verification techniques cannot guarantee that first silicon is designed error free. Because of this reality, there is a need for a good debug methodology. This paper describes the application of a generic silicon debug methodology to a modular video-processing chip called co-processor array (CPA). The debug hardware, which was added to the design, and the supporting debugger software are described. The application of the added debug functionality and its effectiveness during first silicon bring-up are also presented.

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Goel SVermeulen B(2019)Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System ChipsJournal of Electronic Testing: Theory and Applications10.1023/A:102463992585219:4(407-416)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1024639925852
Goossens KVermeulen BSteeden RBennebroek M(2007)Transaction-Based Communication-Centric DebugProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.46(95-106)Online publication date: 7-May-2007
https://dl.acm.org/doi/10.1109/NOCS.2007.46
Marinissen EVermeulen BMadge RKessler MMuller M(2003)Creating Value Through TestProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022761Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022761
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Silicon debug of a co-processor array for video applications
1. Hardware

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Published In

HLDVT '00: Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)

November 2000

ISBN:0769507867

Publisher

IEEE Computer Society

United States

Publication History

Published: 08 November 2000

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Goel SVermeulen B(2019)Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System ChipsJournal of Electronic Testing: Theory and Applications10.1023/A:102463992585219:4(407-416)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1024639925852
Goossens KVermeulen BSteeden RBennebroek M(2007)Transaction-Based Communication-Centric DebugProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.46(95-106)Online publication date: 7-May-2007
https://dl.acm.org/doi/10.1109/NOCS.2007.46
Marinissen EVermeulen BMadge RKessler MMuller M(2003)Creating Value Through TestProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022761Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022761
Vermeulen BOostdijk SBouwman F(2001)Test and Debug Strategy of the PNX8525 Nexperia" Digital Video Platform System ChipProceedings of the 2001 IEEE International Test Conference10.5555/839296.843710Online publication date: 30-Oct-2001
https://dl.acm.org/doi/10.5555/839296.843710

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