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10.5555/549928.795734guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Acceleration of an FPGA router

Published: 16 April 1997 Publication History

Abstract

The authors describe their experience and progress in accelerating an FPGA router. Placement and routing is undoubtedly the most time-consuming process in automatic chip design or configuring programmable logic devices as reconfigurable computing elements. Their goal is to accelerate routing of FPGAs by 10 fold with a combination of processor clusters and hardware acceleration. Coarse-grain parallelism is exploited by having several processors route separate groups of nets in parallel. A hardware accelerator is presented which exploits the fine-grain parallelism in routing individual nets.

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  • (2015)Accelerate FPGA Routing with Parallel Recursive PartitioningProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840836(118-125)Online publication date: 2-Nov-2015
  • (2014)Parallel FPGA Routing based on the Operator FormulationProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593177(1-6)Online publication date: 1-Jun-2014
  • (2003)Stochastic, spatial routing for hypergraphs, trees, and meshesProceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays10.1145/611817.611830(78-87)Online publication date: 23-Feb-2003
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Published In

cover image Guide Proceedings
FCCM '97: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
April 1997
ISBN:0818681594

Publisher

IEEE Computer Society

United States

Publication History

Published: 16 April 1997

Author Tags

  1. FPGA router acceleration
  2. automatic chip design
  3. coarse-grain parallelism
  4. field programmable gate arrays
  5. fine-grain parallelism
  6. hardware acceleration
  7. placement
  8. processor clusters
  9. programmable logic device configuration
  10. reconfigurable computing elements
  11. routing

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Cited By

View all
  • (2015)Accelerate FPGA Routing with Parallel Recursive PartitioningProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840836(118-125)Online publication date: 2-Nov-2015
  • (2014)Parallel FPGA Routing based on the Operator FormulationProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593177(1-6)Online publication date: 1-Jun-2014
  • (2003)Stochastic, spatial routing for hypergraphs, trees, and meshesProceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays10.1145/611817.611830(78-87)Online publication date: 23-Feb-2003
  • (2001)LRouteProceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays10.1145/360276.360290(12-20)Online publication date: 1-Feb-2001
  • (2000)New parallelization and convergence results for NCProceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays10.1145/329166.329201(165-174)Online publication date: 1-Feb-2000

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