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Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions

Author:

Michael C. McFarlandAuthors Info & Claims

DAC '86: Proceedings of the 23rd ACM/IEEE Design Automation Conference

Pages 474 - 480

Published: 02 July 1986 Publication History

Abstract

This paper reports on a new method for using bottom-up design information in the synthesis of integrated circuits from abstract behavioral descriptions. There are two important ways in which this method differs from traditional top-down synthesis techniques. First, it draws on a newly developed procedural database to collect detailed information on the physical and logical properties of the primitives available for building the design. Second, it uses a different method for representing and organizing knowledge about a design that makes possible estimates of physical placement and wiring in the analysis of that design, even at the abstract register-transfer level. This allows a more accurate evaluation of candidate register-transfer designs without doing a full logic-level or transistor-level layout. It also leads to a simple method for systematically exploring the space of possible designs in order to find the one that best meets the designer's objectives and constraints.

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Cited By

Kritikakou ACatthoor FKelefouras VGoutis C(2013)A systematic approach to classify design-time global scheduling techniquesACM Computing Surveys10.1145/2431211.243121345:2(1-30)Online publication date: 12-Mar-2013
https://dl.acm.org/doi/10.1145/2431211.2431213
Wang LJiang YSelvaraj H(2006)Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply VoltagesThe Journal of Supercomputing10.1007/s11227-006-0140-y35:1(93-113)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.1007/s11227-006-0140-y
Kao PHsieh CWu AGoto S(2001)An RTL design-space exploration method for high-level applicationsProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370313(162-168)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370313
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Index Terms

Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '86: Proceedings of the 23rd ACM/IEEE Design Automation Conference

July 1986

835 pages

ISBN:0818607025

Chairman:
Don Thomas
IBM, Thomas J. Watson Research Center, Yorktown Heights, NY

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press

Publication History

Published: 02 July 1986

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DAC '86 Paper Acceptance Rate 124 of 300 submissions, 41%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

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Cited By

Kritikakou ACatthoor FKelefouras VGoutis C(2013)A systematic approach to classify design-time global scheduling techniquesACM Computing Surveys10.1145/2431211.243121345:2(1-30)Online publication date: 12-Mar-2013
https://dl.acm.org/doi/10.1145/2431211.2431213
Wang LJiang YSelvaraj H(2006)Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply VoltagesThe Journal of Supercomputing10.1007/s11227-006-0140-y35:1(93-113)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.1007/s11227-006-0140-y
Kao PHsieh CWu AGoto S(2001)An RTL design-space exploration method for high-level applicationsProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370313(162-168)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370313
Blickle TTeich JThiele L(1998)System-Level Synthesis Using Evolutionary AlgorithmsDesign Automation for Embedded Systems10.1023/A:10088992298023:1(23-58)Online publication date: 1-Jan-1998
https://dl.acm.org/doi/10.1023/A%3A1008899229802
Teich JBlickle TThiele L(1997)An evolutionary approach to system-level synthesisProceedings of the 5th International Workshop on Hardware/Software Co-Design10.5555/792768.793501Online publication date: 24-Mar-1997
https://dl.acm.org/doi/10.5555/792768.793501
Xu MKurdahi F(1997)RTL Synthesis with Physical and Controller InformationProceedings of the 1997 European conference on Design and Test10.5555/787260.787678Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787678
Xu MKurdahi F(1996)Layout-driven RTL binding techniques for high-level synthesisProceedings of the 9th international symposium on System synthesis10.5555/524431.857928Online publication date: 6-Nov-1996
https://dl.acm.org/doi/10.5555/524431.857928
Papachristou CNourani MSymonds GNebel W(1996)False path exclusion in delay analysis of RTL-based datapath-controller designsProceedings of the conference on European design automation10.5555/252471.252530(336-341)Online publication date: 20-Sep-1996
https://dl.acm.org/doi/10.5555/252471.252530
Frank ELengauer TRudell R(1995)APPlaUSEProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225137(662-667)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225137
Zhao WPapachristou CRudell R(1995)Architectural partitioning of control memory for application specific programmable processorsProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225105(521-526)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225105
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