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Memory bank and register allocation in software synthesis for ASIPs

Published: 01 December 1995 Publication History

Abstract

An architectural feature commonly found in digital signal processors (DSPs) is multiple data-memory banks. This feature increases memory bandwidth by permitting multiple memory accesses to occur in parallel when the referenced variables belong to different memory banks and the registers involved are allocated according to a strict set of conditions. Unfortunately, current compiler technology is unable to take advantage of the potential increase in parallelism offered by such architectures. Consequently, most application software for DSP systems is hand-written -- a very time-consuming task.We present an algorithm which attempts to maximize the benefit of this architectural feature. While previous approaches have decoupled the phases of register allocation and memory bank assignment, our algorithm performs these two phases simultaneously. Experimental results demonstrate that our algorithm substantially improves the code quality of many compiler-generated and even hand-written programs.

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  • (2013)Minimizing code size via page selection optimization on partitioned memory architecturesProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555741(1-10)Online publication date: 29-Sep-2013
  • (2008)Minimal placement of bank selection instructions for partitioned memory architecturesACM Transactions on Embedded Computing Systems10.1145/1331331.13313367:2(1-32)Online publication date: 29-Jan-2008
  • (2006)Minimizing bank selection instructions for partitioned memory architectureProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176786(201-211)Online publication date: 22-Oct-2006
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Published In

cover image ACM Conferences
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
December 1995
748 pages
ISBN:0818672137

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IEEE Computer Society

United States

Publication History

Published: 01 December 1995

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ICCAD '95
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ICCAD '95: International Conference on Computer Aided Design
November 5 - 9, 1995
California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (2013)Minimizing code size via page selection optimization on partitioned memory architecturesProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555741(1-10)Online publication date: 29-Sep-2013
  • (2008)Minimal placement of bank selection instructions for partitioned memory architecturesACM Transactions on Embedded Computing Systems10.1145/1331331.13313367:2(1-32)Online publication date: 29-Jan-2008
  • (2006)Minimizing bank selection instructions for partitioned memory architectureProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176786(201-211)Online publication date: 22-Oct-2006
  • (2003)Embedded intelligent SRAMProceedings of the 40th annual Design Automation Conference10.1145/775832.776051(869-874)Online publication date: 2-Jun-2003
  • (2003)An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processorsACM SIGARCH Computer Architecture News10.1145/773365.77337131:1(49-59)Online publication date: 1-Mar-2003
  • (2002)A Framework for Parallelizing Load/Stores on Embedded ProcessorsProceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques10.5555/645989.674319Online publication date: 22-Sep-2002
  • (2002)Design of a high-throughput low-power IS95 Viterbi decoderProceedings of the 39th annual Design Automation Conference10.1145/513918.513988(263-268)Online publication date: 10-Jun-2002
  • (2001)A retargetable compilation methodology for embedded digital signal processors using a machine-dependent code optimizaton libraryReadings in hardware/software co-design10.5555/567003.567047(506-515)Online publication date: 1-Jun-2001
  • (2001)Instruction selection using binate covering for code size optimizationReadings in hardware/software co-design10.5555/567003.567046(499-505)Online publication date: 1-Jun-2001
  • (2001)Embedded software in real-time signal processing systemsReadings in hardware/software co-design10.5555/567003.567041(433-451)Online publication date: 1-Jun-2001
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