Timing yield optimization via discrete gate sizing using globally-informed delay PDFs

We develop two novel globally-informed gate-sizing algorithms for tackling the problems of statistical circuit timing optimization under a timing yield constraint, and timing yield optimization under a timing (i.e., delay) constraint. Unlike previous works, our techniques are global in the sense that they use objective functions that take into account either the entire circuit's variabilities and available gate sizes or those of the statistically timing-critical part of the circuit. The actual optimization, using the aforementioned objective functions, was performed using a recently introduced efficient discrete optimization technique called discretized network flow (DNF). We compared our algorithms to a state-of-the-art sensitivity based method. Experimental results show an absolute yield improvement of up to 43% and an average of 37% for the best of our two techniques over that of a non-statistical timing optimized circuit (optimized using a recent state-of-the-art method) based on the worst-case delay estimate for each gate. Our technique also gives a 19% better relative yield improvement over the sensitivity based method.