Algorithms and hardware architectures for variable block size motion estimation

Multimedia has become more and more important in embedded systems. It is well-known that motion estimation plays an essential role in video coding. It is also one of the key elements that achieve video compression by exploiting temporal redundancy of video data. The latest coding standard H.264 has adopted lots of new features. For instance, in order to adaptively choose the proper block size for frame macroblock, H.264 has used variable block size motion estimation which can significantly improve the coding performance compared to previous techniques. However, the computational complexity of H.264 has also increased drastically. Among all the techniques in the encoder, motion estimation is exactly the most time-consuming function especially when it is implemented in a software approach. In this paper, we combine software and hardware optimizations for variable block size motion estimation. At the software level, we propose a new algorithm that can efficiently select a suitable block size by grouping the motion vectors. At the hardware level, we propose a pipelined and parallel architecture to enhance the performance. Our architecture is implemented on an FPGA platform. It operates at a maximum clock frequency of 311 MHz with gate count 65k. The results show that under a frequency of 248MHz, our architecture allows the processing of 1920x1080 at 30fps with full search motion estimation in a 16x16 search range. This proposed architecture provides a better hardware efficiency in terms of throughput and gate count than previous works.