Article

Free access

Embedded system synthesis by timing constraints solving

Author:

Krzysztof KuchcinskiAuthors Info & Claims

ISSS '97: Proceedings of the 10th international symposium on System synthesis

Pages 50 - 57

Published: 17 September 1997 Publication History

PDF eReader Publisher Site

Abstract

This paper presents an approach to embedded system synthesis which minimizes a system cost while implementing given timing requirements. The embedded system is represented by a set of finite domain constraints defining different requirements on processes timing, system resources and interprocess communication. The assignment of processes to processors and interprocess communications to buses as well as their scheduling are then defined as an optimization problem. A prototype system, based on constraint solving techniques, has been implemented in CHIP 5, the constraint logic programming system. Experimental results show that this approach can be efficiently used to define different system constraints and generate optimized system implementations.

References

[1]

T. Amon and G. Boriello, An Approach to Symbolic Timing Verification, 29th ACM/IEEE Design Automation Conference, pp. 410-413, 1992.

Digital Library

Google Scholar

[2]

A. Bender, Design an Optimal Loosely Coupled Heterogeneous Multiprocessor System, Proc. The European Design and test Conference, March 11-14, 1996, Paris, France, p. 275-281.

Digital Library

Google Scholar

[3]

LI. Bierkcr and P. Marwedcl, Retargetable Self-Test Program Generation Using Constraint Logic Programming, 32nd ACM/IEEE Design Automation Conference, pp. 605-611.

Digital Library

Google Scholar

[4]

CHIP, System Documentation, COSYTEC, 1996.

Google Scholar

[5]

P. Eles, Z. Peng, K. Kuch~insld and A. Doboli, System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search, Design Automation for Embedded Systems Journal, vol. 2, no. 1, January 1997.

Google Scholar

[6]

R. Ernst, J. Henkel, T. Benncr, Hardware-Software Co- Synthesis for Microcontrollers, IEEE Design & Test of Computers, September 1993, pp. 64-75.

Digital Library

Google Scholar

[7]

D.D. Gajski, F. Vahid, Specification and Design of Embedded Hardware-Software Systems, IEEE Design & Test of Computers, Spring 1995, pp. 53-67.

Digital Library

Google Scholar

[8]

P. Girodias and E. Cemy, Interface Timing Verification with Delay Correlation Using Constraint Logic Programming, Proc. European Design and Test Conference, March 17-20, 1997, Pads, France.

Digital Library

Google Scholar

[9]

R.K. Gupta and G. de Michdi, A Co-Synthesis Approach to Embedded System Design Automation, Design Automation for Embedded Systems Journal, voL 1, no. I-2, January 1996.

Digital Library

Google Scholar

[10]

K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, Inc., 1993.

Digital Library

Google Scholar

[11]

D. Ku and G. De Mieheli, Relative Scheduling trader Timing Constraints: Algorithms for High-Level Synthesis of Digital Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 6, June 1992.

Crossref

Google Scholar

[12]

S. Prakash and A. Parker, SOS: Synthesis of Application- Specific Heterogeneous Multiprocessor Systems, Journal of Parallel and Distributed Computing, 16, 1992.

Google Scholar

[13]

S. Prakash and A. Parker, Synthesis of Application-Specific Multiprocessor Systems Including Memory Components, Journal of VLSI Signal Processing, 8, 1994.

Digital Library

Google Scholar

[14]

W. H. Wolf, Hardware-Software Co-Design of Embedded Systems, Proceedings of the IEEE, vol. 82, no. 7, July 1994, pp. 967-989.

Crossref

Google Scholar

Cited By

View all

Pop TPop PEles PPeng Z(2019)Analysis and optimisation of hierarchically scheduled multiprocessor embedded systemsInternational Journal of Parallel Programming10.1007/s10766-007-0059-936:1(37-67)Online publication date: 27-Jan-2019
https://dl.acm.org/doi/10.1007/s10766-007-0059-9
Zhang ZChan WTse TLu HMei L(2009)Resource prioritization of code optimization techniques for program synthesis of wireless sensor network applicationsJournal of Systems and Software10.1016/j.jss.2009.05.01882:9(1376-1387)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1016/j.jss.2009.05.018
Vahid FGivargis TGebotys CMartin G(2008)Highly-cited ideas in system codesign and synthesisProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450178(191-196)Online publication date: 19-Oct-2008
https://dl.acm.org/doi/10.1145/1450135.1450178
Show More Cited By

Recommendations

A framework for interactive analysis of timing constraints in embedded systems
CODES '96: Proceedings of the 4th International Workshop on Hardware/Software Co-Design

An important goal of embedded system co-synthesis is to realize system designs under constraints on timing performance. We present applicable constraints and the notion of satisfiability of a given set of constraints. We describe a two-level system ...
Feasibility of semiring-based timing constraints

Real-time and embedded applications often involve different types of timing constraints, such as precedence constraints and real-time constraints. As real-time and embedded applications further advance, new timing constraint types are emerging as well. ...
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems

In high-level synthesis for real-time embedded systems using heterogeneous functional units (FUs), it is critical to select the best FU type for each task. However, some tasks may not have fixed execution times. This article models each varied execution ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ISSS '97: Proceedings of the 10th international symposium on System synthesis

September 1997

141 pages

ISBN:0818679492

Chairmen:
Frank Vahid
Univ. of California, Riverside
,
Francky Catthoor
IMEC, Leuven, Belgium

Publisher

IEEE Computer Society

United States

Publication History

Published: 17 September 1997

Check for updates

Author Tags

Qualifiers

Article

Conference

ISSS97

Sponsor:

SIGDA
IEEE-CS

ISSS97: 10th Internatioanl Symposium on System Synthesis

September 17 - 19, 1997

Antwerp, Belgium

Acceptance Rates

Overall Acceptance Rate 38 of 71 submissions, 54%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

14
Total Citations
View Citations
317
Total Downloads

Downloads (Last 12 months)36
Downloads (Last 6 weeks)6

Reflects downloads up to 11 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Pop TPop PEles PPeng Z(2019)Analysis and optimisation of hierarchically scheduled multiprocessor embedded systemsInternational Journal of Parallel Programming10.1007/s10766-007-0059-936:1(37-67)Online publication date: 27-Jan-2019
https://dl.acm.org/doi/10.1007/s10766-007-0059-9
Zhang ZChan WTse TLu HMei L(2009)Resource prioritization of code optimization techniques for program synthesis of wireless sensor network applicationsJournal of Systems and Software10.1016/j.jss.2009.05.01882:9(1376-1387)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1016/j.jss.2009.05.018
Vahid FGivargis TGebotys CMartin G(2008)Highly-cited ideas in system codesign and synthesisProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450178(191-196)Online publication date: 19-Oct-2008
https://dl.acm.org/doi/10.1145/1450135.1450178
Jówiak LOng S(2008)Quality-driven model-based architecture synthesis for real-time embedded SoCsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2007.09.00154:3-4(349-368)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1016/j.sysarc.2007.09.001
Bouyssounouse BSifakis J(2005)Computing platformsEmbedded Systems Design10.5555/2137690.2137723(388-449)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/2137690.2137723
Subramani K(2005)Periodic Linear Programming with applications to real-time schedulingMathematical Structures in Computer Science10.1017/S096012950400465715:2(383-406)Online publication date: 1-Apr-2005
https://dl.acm.org/doi/10.1017/S0960129504004657
Xie YWolf W(2001)Allocation and scheduling of conditional task graph in hardware/software co-synthesisProceedings of the conference on Design, automation and test in Europe10.5555/367072.367835(620-625)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367835
Szymanek RKuchcinski KMadsen JHenkel JHu X(2001)A constructive algorithm for memory-aware task assignment and schedulingProceedings of the ninth international symposium on Hardware/software codesign10.1145/371636.371706(147-152)Online publication date: 25-Apr-2001
https://dl.acm.org/doi/10.1145/371636.371706
Kuchcinski K(1999)Integrated resource assignment and scheduling of task graphs using finite domain constraintsProceedings of the conference on Design, automation and test in Europe10.1145/307418.307494(47-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307494
Pop PEles PPeng ZJerraya ALavagno LVahid F(1999)Scheduling with optimized communication for time-triggered embedded systemsProceedings of the seventh international workshop on Hardware/software codesign10.1145/301177.303812(178-182)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1145/301177.303812
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

A framework for interactive analysis of timing constraints in embedded systems

Feasibility of semiring-based timing constraints

Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems