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Energy minimization using multiple supply voltages

Published: 12 August 1996 Publication History
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References

[1]
R. Burch, F. Najm, P. Yang and T. Trick, "A Monte Carlo approach for power estimation". In IEEE Trans. on VLSI page 63-61, March 1993.
[2]
R. Camposanoand and W. Wolf, "High-level VLSI synthesis", PP. 256, Kluwer Academic Publishers, 1991.
[3]
A. Chandrakasan, M. Potkonjak, J. Rabaey, and R.W. Brodersen,"HYPER-LP: A System for Power Minimization Using Architectural Transformations", In Proceedings of the ICCAD 1992.
[4]
J.-M. Chang and M. Pedram, "How to Minimize Energy Using Multiple Supply Voltages", CENG Technical Report 96-13, Computer Engineering Division, Dept. of EE- Systems, Univ. of Southern California, 1996.
[5]
K. Chaudhary and M. Pedram, "Computing the area versus delay trade-off curves in technology mapping", In Proceedings of the IEEE Transactions on CAD, v14, n12, Dec 1995.
[6]
C. Deng, Power Analysis for CMOS/BiCMOS circuits. In Proceedingss of the 1994 International Workshop on Low Power Design, pages 3-8, April 1994.
[7]
M. Garey and D. Johnson, "Computers and Intractability: A Guide to the Theory of NP-completeness", W. H. Freeman and Company, 1979.
[8]
C. Gebotys and M. Elmasry, "Optimal VLSI Architectural Synthesis", Kluwer Academic Publishcation, pp. 148, 1992.
[9]
M. Golumbic, "Algorithmic Graph Theory and Perfect Graphs", Academic Press, 1980.
[10]
S. Haykin, "Adaptive Filter Theory", 2nd edition, Chap5, 6, and 8, Printice Hall, 1991.
[11]
P. Landman and J. Rabaey, "Black-Box Capacitance Models for Architectural Power Analysis", In Proceedings of the 1994 International Workshop Low Power Design, April 1994.
[12]
W.-N. Li, A. Lim, P. Agrawal and S. Sahni, "On The Circuit Implementation Problem", In Proceedings of the 29th DAC, June 1992.
[13]
R. Mehra and J. Rabaey. "Behavioral Level Power Estimation and Exploration.", In Proceedings of the 1994 International Workshop on Low Power Design, pp. 197-202, Apr, 1994.
[14]
R. Powell and M. Chau, "A Model for Estimating Power Dissipation in a Class of DSP VLSI Chips", In IEEE Trans. on Circuits and Systems, Vol 38, No. 6, June 1991.
[15]
N. Park, A. Parker,"Sehwa: A Software Package for Synthesis of Pipelines from behavioral Specifications", In IEEE Trans. on CAD, vol 7, no. 3, March 1988.
[16]
S. Raje, M. Sarrafzadeh, "Variable Voltage Scheduling", In Proceedings of the 1995 International Workshop Low Power Design, 1995
[17]
L. Stok, "Architectural Synthesis and Optimization of Digital Systems", Ph.D Dissertation, Eindhoven University of Technology, 1991.
[18]
C. Svensson and D. Liu, "A Power Estimation Tool and Prospects of Power Savings in CMOS VLSI Chips". In Proceedings of the 1994 International Workshop on Low Power Design, pp. 171-176, Apr 1994.
[19]
H. Toutai, W. Moon, R. Brayton, and A. Wang. "Performance-oriented technology mapping". In Proceedings of the Sixth M.I.T. Conference on Advanced Research in VLSI, pp. 79-97, Apr. 1990.
[20]
C.-Y. Tsui, M. Pedram, and A. Despain, "Power Efficient Technology Decomposition and Mapping Under and Extended Power Consumption Model", in IEEE trans, on CAD, vol. 13, No. 9, Sep 1994.
[21]
K. Usami and M. Horowitz, "Clustered Voltage Scaling Technique for Low-Power Design", in Proceedings of the 1995 International Workshop on Low Power Design, pp. 3-8, 1995

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  • (2010)Clustering-based simultaneous task and voltage scheduling for NoC systemsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133488(277-283)Online publication date: 7-Nov-2010
  • (2007)Power deregulationProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289844(105-110)Online publication date: 30-Sep-2007
  • (2006)Voltage island aware floorplanning for power and timing optimizationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233579(389-394)Online publication date: 5-Nov-2006
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cover image ACM Conferences
ISLPED '96: Proceedings of the 1996 international symposium on Low power electronics and design
August 1996
390 pages

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Published: 12 August 1996

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Cited By

View all
  • (2010)Clustering-based simultaneous task and voltage scheduling for NoC systemsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133488(277-283)Online publication date: 7-Nov-2010
  • (2007)Power deregulationProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289844(105-110)Online publication date: 30-Sep-2007
  • (2006)Voltage island aware floorplanning for power and timing optimizationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233579(389-394)Online publication date: 5-Nov-2006
  • (2004)High level techniques for power-grid noise immunityProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.988957(13-18)Online publication date: 26-Apr-2004
  • (2004)Energy-efficient dual-voltage soft real-time system with (m,k)-firm deadline guaranteeProceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1023833.1023850(116-123)Online publication date: 22-Sep-2004
  • (2004)Power minimization in QoS sensitive systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82756712:6(553-561)Online publication date: 1-Jun-2004
  • (2003)Approaching the Maximum Energy Saving on Embedded Systems with Multiple VoltagesProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009864Online publication date: 9-Nov-2003
  • (2003)An on-line approach for power minimization in QoS sensitive systemsProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119785(59-64)Online publication date: 21-Jan-2003
  • (2002)Minimizing Energy Consumption for High-Performance ProcessingProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835488Online publication date: 7-Jan-2002
  • (2002)Enhanced clustered voltage scaling for low powerProceedings of the 12th ACM Great Lakes symposium on VLSI10.1145/505306.505311(18-23)Online publication date: 18-Apr-2002
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