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Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm

Published: 01 January 1997 Publication History

Abstract

Lucent TechnologiesThis paper discusses the analysis of large linear electrical networks consisting of passive components, such as resistors, capacitors, inductors, and transformers. Such networks admit a symmetric formulation of their circuit equations. We introduce SyPVL, an efficient and numerically stable algorithm for the computation of reduced-order models of large, linear, passive networks. SyPVL represents the specialization of the more general PVL algorithm, to symmetric problems. Besides the gain in efficiency over PVL, SyPVL also preserves the symmetry of the problem, and, as a consequence, can often guarantee the stability of the resulting reduced-order models. Moreover, these reduced-order models can be synthesized as actual physical circuits, thus facilitating compatibility with existing analysis tools. The application of SyPVL is illustrated with two interconnect-analysis examples.

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  • (2006)Parallel solution of large-scale and sparse generalized algebraic riccati equationsProceedings of the 12th international conference on Parallel Processing10.1007/11823285_74(710-719)Online publication date: 28-Aug-2006
  • (2005)Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reductionProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120811(224-229)Online publication date: 18-Jan-2005
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Published In

cover image ACM Conferences
ICCAD '96: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
January 1997
703 pages
ISBN:0818675977

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IEEE Computer Society

United States

Publication History

Published: 01 January 1997

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Author Tags

  1. Lanczos algorithm
  2. Pade approximations
  3. interconnect
  4. network synthesis
  5. passive networks
  6. reduced-order modeling
  7. symmetric formulation

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ICCAD '96
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ICCAD '96: International Conference on Computer Aided Design
November 10 - 14, 1996
California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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  • (2007)Fast positive-real balanced truncation of symmetric systems using cross Riccati equationsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266695(1496-1501)Online publication date: 16-Apr-2007
  • (2006)Parallel solution of large-scale and sparse generalized algebraic riccati equationsProceedings of the 12th international conference on Parallel Processing10.1007/11823285_74(710-719)Online publication date: 28-Aug-2006
  • (2005)Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reductionProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120811(224-229)Online publication date: 18-Jan-2005
  • (2004)SPRIMProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382547(80-87)Online publication date: 7-Nov-2004
  • (2004)Parallel algorithms for balanced truncation model reduction of sparse systemsProceedings of the 7th international conference on Applied Parallel Computing: state of the Art in Scientific Computing10.1007/11558958_32(267-275)Online publication date: 20-Jun-2004
  • (2003)A General S-Domain Hierarchical Network Reduction AlgorithmProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009958Online publication date: 9-Nov-2003
  • (2003)Improved model-order reduction by using spacial information in momentsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81713811:5(900-908)Online publication date: 1-Oct-2003
  • (2002)Efficient model order reduction via multi-node moment matchingProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774685(767-774)Online publication date: 10-Nov-2002
  • (2002)Aggressive crunching of extracted RC netlistsProceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems10.1145/589411.589426(70-77)Online publication date: 2-Dec-2002
  • (2001)Mixed-Technology System-Level SimulationAnalog Integrated Circuits and Signal Processing10.1023/A:101129461683129:1-2(127-149)Online publication date: 15-Oct-2001
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