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The performance potential of data dependence speculation & collapsing

Authors:

Yiannakis Sazeides,

Stamatis Vassiliadis,

James E. SmithAuthors Info & Claims

MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture

Pages 238 - 247

Published: 02 December 1996 Publication History

Abstract

Two hardware methods for remedying the effects of true data dependences are studied. The first method dependence speculation, is used to eliminate address generation-load dependences. This is enabled by address prediction that permits load instructions to proceed speculatively without waiting for their address operands. The second technique, dependence collapsing, is used to eliminate data dependences by combining a dependence among multiple instructions into one instruction. The potential of these techniques for improving processor performance is demonstrated via trace-driven simulation. When both techniques are used with maximum issue widths of 4, 8, 16, and 32, the overall speedups in comparison to a base instruction level parallel machine are 1.20, 1.35, 1.51, and 1.66, respectively. In general, dependence collapsing contributes the majority of the improvement in performance. Under the dependence collapsing model, 298 to 478 of the total number of instructions in a trace may be collapsed. The distance separating the collapsed instructions is nearly always less than 8. Our experimentation also suggests that further performance improvements can be achieved by incorporating mechanisms that increase the address prediction rate.

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Cited By

Orosa LAzevedo RMutlu O(2018)AVPPACM Transactions on Architecture and Code Optimization10.1145/323956715:4(1-30)Online publication date: 7-Dec-2018
https://dl.acm.org/doi/10.1145/3239567
Sheikh RCain HDamodaran RHunter HMoreno JEmer JSanchez D(2017)Load value prediction via path-based address predictionProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123951(423-435)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123951
Ghandour WAkkary HMasri W(2012)Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value PredictionACM Transactions on Architecture and Code Optimization10.1145/2133382.21333839:1(1-33)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1145/2133382.2133383
Show More Cited By

Index Terms

The performance potential of data dependence speculation & collapsing
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
2. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

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Information & Contributors

Information

Published In

cover image ACM Conferences

MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture

December 1996

359 pages

ISBN:0818676418

Chairmen:
Stephen Melvin
Zytek Communications Corp.
,
Steve Beaty
Hewlett-Packard Corp.

Copyright © Copyright (c) 1996 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE-CS\TCMM: TC on Microprocessors & Microcomputers

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IEEE Computer Society

United States

Publication History

Published: 02 December 1996

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MICRO96

Sponsor:

SIGMICRO
IEEE-CS\TCMM

MICRO96: 29th Annual International Symposium on Microarchitecture

December 2 - 4, 1996

Paris, France

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

Orosa LAzevedo RMutlu O(2018)AVPPACM Transactions on Architecture and Code Optimization10.1145/323956715:4(1-30)Online publication date: 7-Dec-2018
https://dl.acm.org/doi/10.1145/3239567
Sheikh RCain HDamodaran RHunter HMoreno JEmer JSanchez D(2017)Load value prediction via path-based address predictionProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123951(423-435)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123951
Ghandour WAkkary HMasri W(2012)Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value PredictionACM Transactions on Architecture and Code Optimization10.1145/2133382.21333839:1(1-33)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1145/2133382.2133383
Dasika GWoh MSeo SClark NMudge TMahlke SKathail VTatge RBarua R(2010)Mighty-morphing power-SIMDProceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1878921.1878934(67-76)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878921.1878934
Ghandour WAkkary HMasri WSalapura VGschwind MKnoop J(2010)The potential of using dynamic information flow analysis in data value predictionProceedings of the 19th international conference on Parallel architectures and compilation techniques10.1145/1854273.1854327(431-442)Online publication date: 11-Sep-2010
https://dl.acm.org/doi/10.1145/1854273.1854327
Trias APuiggalí JCastro FJové TSbert MMarzo J(2009)Speculative parallelization of multipath radiosity algorithmProceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems10.5555/1688291.1688305(89-95)Online publication date: 13-Jul-2009
https://dl.acm.org/doi/10.5555/1688291.1688305
Yehia SClark NMahlke SFlautner KConte TFaraboschi PMangione-Smith BNajjar W(2005)Exploring the design space of LUT-based transparent acceleratorsProceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1086297.1086301(11-21)Online publication date: 24-Sep-2005
https://dl.acm.org/doi/10.1145/1086297.1086301
Clark NBlome JChu MMahlke SBiles SFlautner K(2005)An Architecture Framework for Transparent Instruction Set Customization in Embedded ProcessorsACM SIGARCH Computer Architecture News10.1145/1080695.106999333:2(272-283)Online publication date: 1-May-2005
https://dl.acm.org/doi/10.1145/1080695.1069993
Clark NBlome JChu MMahlke SBiles SFlautner K(2005)An Architecture Framework for Transparent Instruction Set Customization in Embedded ProcessorsProceedings of the 32nd annual international symposium on Computer Architecture10.1109/ISCA.2005.9(272-283)Online publication date: 4-Jun-2005
https://dl.acm.org/doi/10.1109/ISCA.2005.9
Yehia STemam O(2004)From Sequences of Dependent Instructions to FunctionsProceedings of the 31st annual international symposium on Computer architecture10.5555/998680.1006721Online publication date: 19-Jun-2004
https://dl.acm.org/doi/10.5555/998680.1006721
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