research-article

A 12-Gb/s DEMUX Implemented with SiGe high-speed FPGA circuits

Authors:

John F. McdonaldAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, Issue 9

Pages 1051 - 1054

Published: 01 September 2007 Publication History

Abstract

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

References

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Tomasi MVanegas MBarranco FDíaz JRos E(2018)Real-time architecture for a robust multi-scale stereo engine on FPGAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217200720:12(2208-2219)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2011.2172007

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A 12-Gb/s DEMUX Implemented with SiGe high-speed FPGA circuits
1. Hardware

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 15, Issue 9

September 2007

83 pages

ISSN:1063-8210

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IEEE Educational Activities Department

United States

Publication History

Published: 01 September 2007

Revised: 19 March 2007

Received: 23 November 2004

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Tomasi MVanegas MBarranco FDíaz JRos E(2018)Real-time architecture for a robust multi-scale stereo engine on FPGAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217200720:12(2208-2219)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2011.2172007

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Recommendations

Special purpose FPGA for high-speed digital telecommunication systems

An improved high speed, and low voltage CMOS current mode logic latch

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

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