An Automated, Complete, Structural Test Solution for SERDES

Gigahertz serialization and deserialization (SERDES) has become a dominant inter-chip and interboard data transmission technique. Signal integrity is the primary factor determining its bit error rate, typically less than 10-12, so the primary production test challenges are testing picosecond jitter and the signal eye opening. Off-chip jitter and rise/fall time measurements are limited by hardware complexity, access, bandwidth, and noise. Published on-chip measurement techniques are limited by delay line jitter. This paper presents a new jitter test technique that has been demonstrated on an FPGA to achieve less than 1 ps RMS self-jitter, and a new signal eye test that has unlimited bandwidth; neither test uses high speed circuitry. The all-digital technique uses the receiver itself to demodulate the signal jitter to a low-speed bit stream that is analyzed by a single-clock domain, synthesizable circuit. This is combined with logic BIST and 1149.6 boundary scan to completely test an IC.