Article

Automatic gate-level synthesis of speed-independent circuits

Authors:

P. A. Beerel,

T. H.-Y. MengAuthors Info & Claims

ICCAD '92: 1992 IEEE/ACM international conference proceedings on Computer-aided design

Pages 581 - 586

Published: 01 December 1992 Publication History

Abstract

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Beerel PBurch JMeng T(1998)Checking Combinational Equivalence of Speed-Independent CircuitsFormal Methods in System Design10.1023/A:100866660543713:1(37-85)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1023/A%3A1008666605437
Tabrizi NLiebelt MEshraghian K(1997)A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design MethodologyIEEE Transactions on Computers10.1109/12.62048746:9(1050-1054)Online publication date: 1-Sep-1997
https://dl.acm.org/doi/10.1109/12.620487

Index Terms

Automatic gate-level synthesis of speed-independent circuits
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits
      1. Sequential circuits

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This paper presents a CAD tool for the automatic synthesis of gate-level timed circuits from general specifications to basic gates such as AND gates, OR gates, and C-elements. Timed circuits are a class of asynchronous circuits that incorporate explicit ...
Hierarchical gate-level verification of speed-independent circuits
ASYNC '95: Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C ...

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Information

Published In

ICCAD '92: 1992 IEEE/ACM international conference proceedings on Computer-aided design

December 1992

664 pages

ISBN:0818630108

Chairman:
Louise Trevillyan
IBM Corp., Yorktown Heights, NY

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 December 1992

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Cited By

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Beerel PBurch JMeng T(1998)Checking Combinational Equivalence of Speed-Independent CircuitsFormal Methods in System Design10.1023/A:100866660543713:1(37-85)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1023/A%3A1008666605437
Tabrizi NLiebelt MEshraghian K(1997)A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design MethodologyIEEE Transactions on Computers10.1109/12.62048746:9(1050-1054)Online publication date: 1-Sep-1997
https://dl.acm.org/doi/10.1109/12.620487

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Cited By

Index Terms

Recommendations

Automatic Synthesis of Gate-Level Speed-Independent Circuits

Automatic synthesis of gate-level timed circuits with choice

Hierarchical gate-level verification of speed-independent circuits

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