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Article

Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores

Authors:

Gerald R. Morris,

Viktor K. PrasannaAuthors Info & Claims

IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04

Page 147.1

Published: 04 April 2005 Publication History

Abstract

The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when using single-cycle arithmetic cores. In particular, the data hazards associated with pipelined floating-point reduction circuits can limit the scalability or severely reduce the performance of an otherwise high-performance computational kernel. The inability to efficiently execute the reduction in hardware coupled with memory bandwidth issues may even negate the performance gains derived from hardware acceleration of the kernel. In this paper we introduce a method for developing scalable floating-point reduction circuits that run in optimal time while requiring only (lg (n)) space and a single pipelined floating-point unit. Using a Xilinx Virtex-II Pro as the target device, we implement reference instances of our reduction method and present the FPGA design statistics supporting our scalability claims.

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Cited By

Jin ZFinkel H(2018)A Case Study of Integer Sum Reduction using AtomicsProceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies10.1145/3241793.3241809(1-7)Online publication date: 20-Jun-2018
https://dl.acm.org/doi/10.1145/3241793.3241809
Grigoras PBurovskiy PLuk WChen DGreene J(2016)CASKProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847338(179-184)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847338
Wilson DStitt G(2016)The Unified Accumulator ArchitectureACM Transactions on Reconfigurable Technology and Systems10.1145/28094329:3(1-23)Online publication date: 20-May-2016
https://dl.acm.org/doi/10.1145/2809432
Show More Cited By

Index Terms

Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Pipeline computing
2. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image Guide Proceedings

IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04

April 2005

ISBN:0769523129

Publisher

IEEE Computer Society

United States

Publication History

Published: 04 April 2005

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Cited By

Jin ZFinkel H(2018)A Case Study of Integer Sum Reduction using AtomicsProceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies10.1145/3241793.3241809(1-7)Online publication date: 20-Jun-2018
https://dl.acm.org/doi/10.1145/3241793.3241809
Grigoras PBurovskiy PLuk WChen DGreene J(2016)CASKProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847338(179-184)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847338
Wilson DStitt G(2016)The Unified Accumulator ArchitectureACM Transactions on Reconfigurable Technology and Systems10.1145/28094329:3(1-23)Online publication date: 20-May-2016
https://dl.acm.org/doi/10.1145/2809432
Mish SZenor JCrosbie RVakilzadian HCrosbie RHuntsinger RCooper K(2013)An efficient FPGA matrix multiplier for linear system simulationProceedings of the 2013 Grand Challenges on Modeling and Simulation Conference10.5555/2557668.2557671(1-5)Online publication date: 7-Jul-2013
https://dl.acm.org/doi/10.5555/2557668.2557671
Wang XLeeser M(2010)VFloatACM Transactions on Reconfigurable Technology and Systems10.1145/1839480.18394863:3(1-34)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1145/1839480.1839486
Zhuo LMorris GPrasanna V(2007)High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2007.106818:10(1377-1392)Online publication date: 1-Oct-2007
https://dl.acm.org/doi/10.1109/TPDS.2007.1068
Kwatra APrasanna VSingh M(2006)Accelerating DTI tractography using FPGAsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1899141(194-194)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898953.1899141
Zhuo LPrasanna VSchmit HWilton S(2005)Sparse Matrix-Vector multiplication on FPGAsProceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays10.1145/1046192.1046202(63-74)Online publication date: 20-Feb-2005
https://dl.acm.org/doi/10.1145/1046192.1046202
Zhuo LPrasanna VKramer W(2005)High Performance Linear Algebra Operations on Reconfigurable SystemsProceedings of the 2005 ACM/IEEE conference on Supercomputing10.1109/SC.2005.31Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/SC.2005.31

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