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A new global routing algorithm for FPGAs

Published: 06 November 1994 Publication History

Abstract

As in traditional ASIC technologies, FPGA routing usually consists of two steps: global routing and detailed routing. Unlike existing FPGA detailed routers, which can take full advantage of the special structures of the programmable routing resources, FPGA global routing algorithms still greatly resemble their counterparts in the traditional ASIC technologies. In particular, the routing congestion information of a switch block essentially is still measured by the numbers of available rows and columns in the switch block. Since the internal architecture of a switch block decides what can route through the block, the traditional measure of routing capacity is no longer accurate. In this paper, we present an accurate measure of switch block routing capacity. Our new measure considers the exact positions of the switches inside a switch block. Experiments with a global router based on these ideas show an average improvement of 38% in the channel width required to route some benchmark circuits using a popular switch block, compared with an algorithm based on the traditional methods for congestion control.

References

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N. Bhat and D. Hill, "Routable Technology Mapping for LUT FPGA's," Proc. Intl. Conf. Computer-Aided Design, pp. 95-98, 1992.
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S. Brown, J. Ross, and Z.G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE Trans. Computer-Aided Design, vol. 11, pp. 620-627, 1992.
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W. Carter et al., "A User Programmable Reconfigurable Gate Array," Proc. 1986 Custom Integrated Circuits Conference, May 1986, pp. 233-235, 1986.
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S. Thakur, D.F. Wong, and S. Muthukrishnan, "Algorithms for FPGA Switch Module Routing," Proc. EuroDAC, to appear, 1994.
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S. Trimberger, ed., Field-Programmable Gate Atray Technology, Kluwer Academic Publishers, 1994.
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S. Trimberger and M. Chene, "Placement-Based Partitioning for Lookup-Table-Based FPGA's," Proc. Intl. Conf. Computer-Aided Design, pp. 91- 94, 1992.
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Cited By

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  • (2017)FPGA placement and routingProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199826(914-921)Online publication date: 13-Nov-2017
  • (2012)Networked architecture for hybrid electrical energy storage systemsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228453(522-528)Online publication date: 3-Jun-2012
  • (2005)Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing ResourcesProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.26(232-237)Online publication date: 11-May-2005
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Published In

cover image ACM Conferences
ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
November 1994
771 pages
ISBN:0897916905

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 06 November 1994

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ICCAD '94
Sponsor:
ICCAD '94: International Conference on Computer Aided Design
November 6 - 10, 1994
California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (2017)FPGA placement and routingProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199826(914-921)Online publication date: 13-Nov-2017
  • (2012)Networked architecture for hybrid electrical energy storage systemsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228453(522-528)Online publication date: 3-Jun-2012
  • (2005)Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing ResourcesProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.26(232-237)Online publication date: 11-May-2005
  • (2003)Graph matching-based algorithms for array-based FPGA segmentation design and routingProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119959(851-854)Online publication date: 21-Jan-2003
  • (2000)Timing-driven routing for symmetrical array-based FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/348019.3481015:3(433-450)Online publication date: 1-Jul-2000
  • (2000)An architecture-driven metric for simultaneous placement and global routing for FPGAsProceedings of the 37th Annual Design Automation Conference10.1145/337292.337582(567-572)Online publication date: 1-Jun-2000
  • (2000)Measuring routing congestion for multi-layer global routingProceedings of the 10th Great Lakes symposium on VLSI10.1145/330855.330968(59-62)Online publication date: 2-Mar-2000
  • (1997)FPGA routing and routability estimation via Boolean satisfiabilityProceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays10.1145/258305.258322(119-125)Online publication date: 9-Feb-1997
  • (1995)Performance-driven simultaneous place and route for island-style FPGAsProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225060(332-338)Online publication date: 1-Dec-1995
  • (1995)New performance-driven FPGA routing algorithmsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217589(562-567)Online publication date: 1-Jan-1995

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