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Multi-level placement with circuit schema based clustering in analog IC layouts

Published: 27 January 2004 Publication History

Abstract

This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of clusters from a circuit schema as experts do. We provide a multi-level placement based on the Sequence-Pair by relaxing the shape of clusters from rectangles and allowing boundaries of clusters to be 'jagged'. The quality of placement is evaluated by a multi-objective according to an expert's guideline. We adopt a multi-step simulated annealing to balance a trade-off between the objectives. In experiments, we tested the placement for industrial examples. Our tool attained placements better than those by manual on the average by 10.8% and 6.8% with respect to area and net-length, respectively. It also achieved 1/730 layout time compared with the time by manual.

References

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Seiko Instruments Inc. http://www.sii.co.jp

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cover image ACM Conferences
ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference
January 2004
957 pages
ISBN:0780381750

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IEEE Press

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Published: 27 January 2004

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  • (2018)WB-treesProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196137(1-6)Online publication date: 24-Jun-2018
  • (2016)QB-treesProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898074(1-6)Online publication date: 5-Jun-2016
  • (2013)Practicality on placement given by optimality of packingProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451931(59-60)Online publication date: 24-Mar-2013
  • (2011)A corner stitching compliant B*-tree representation and its applications to analog placementProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132444(507-511)Online publication date: 7-Nov-2011
  • (2010)Regularity-oriented analog placement with diffusion sharing and well island generationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899787(305-311)Online publication date: 18-Jan-2010
  • (2008)Constraint-free analog placement with topological symmetry structureProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356852(186-191)Online publication date: 21-Jan-2008
  • (2008)Analog placement based on hierarchical module clusteringProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391484(50-55)Online publication date: 8-Jun-2008

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