Compaction of two-level microprograms for a multiprocessor computer
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Compaction of two-level microprograms for a multiprocessor computer
MICRO 17: Proceedings of the Seventeenth Annual Microprogramming WorkshopAn optimizing loader has been designed and developed for two-level microprograms of a multiprocessor computer. In the computer, a microinstruction activates nanoprograms in multiprocessors, specifying nanoprogram start address and the processors to be ...
A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions
A two-level microprogrammed multiprocessor system, MUNAP, along with its support software has been developed as a research vehicle for solving nonnumeric and associated problems. The MUNAP system provides highly parallel and distributed functions for ...
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruction-level parallelism (ILP) and thread-level parallelism (TLP). Wide-issue super-scalar processors exploit ILP by executing multiple instructions from a ...
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- Dec. 1984302 pages
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IEEE Press
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