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- research-articleFebruary 2024
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 17, Issue 1Article No.: 17, Pages 1–29https://doi.org/10.1145/3639055A new area model for estimating the layout area of switch blocks is introduced in this work. The model is based on a realistic layout strategy. As a result, it not only takes into consideration the active area that is needed to construct a switch block ...
- research-articleSeptember 2022
The effect of gate voltage boosting on the power efficiency of multi-context FPGAs
Integration, the VLSI Journal (INTG), Volume 86, Issue CPages 30–43https://doi.org/10.1016/j.vlsi.2022.04.007AbstractGate voltage boosting has been routinely used in FPGAs to increase the performance and energy efficiency of pass transistor circuits. The boosting technique is used either alone or in conjunction with level restorers to restore pass ...
Highlights- Investigated different context switching circuits for MC-FPGAs.
- Identified the ...
- research-articleJuly 2022
Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs
Microprocessors & Microsystems (MSYS), Volume 92, Issue Chttps://doi.org/10.1016/j.micpro.2022.104563AbstractSwitch block flexibility is an important design metric in FPGA architectural research. A switch block with high flexibility can provide better routability for implementing digital applications, which can lead to better performance and ...
- research-articleMarch 2018
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 11, Issue 1Article No.: 8, Pages 1–23https://doi.org/10.1145/3182394This work provides an evaluation on the accuracy of the minimum-width transistor area models in ranking the actual layout area of FPGA architectures. Both the original VPR area model and the new COFFE area model are compared against the actual layouts ...
- research-articleJuly 2017
A study on the accuracy of minimum width transistor area in estimating FPGA layout area
Microprocessors & Microsystems (MSYS), Volume 52, Issue CPages 287–298https://doi.org/10.1016/j.micpro.2017.05.020Integrating reconfigurable fabrics in SOCs requires an accurate estimation of the layout area of the reconfigurable fabrics in order to properly optimize the architectural-level design of the fabrics and accommodate early floor-planning. This work ...
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- posterFebruary 2017
Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only)
FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPage 285https://doi.org/10.1145/3020078.3021756This work measures the performance and power consumption gap between the current generation of low power FPGAs and low power microprocessors (microcontrollers) through an implementation of the Canny edge detection algorithm. In particular, the algorithm ...
- articleJuly 2016
Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection
Circuits, Systems, and Signal Processing (CSSP), Volume 35, Issue 7Pages 2487–2501https://doi.org/10.1007/s00034-015-0147-9This paper presents an adaptive decision feedback equalizer (DFE) utilizing a hexagon eye-opening monitor to detect both the violation of the minimum eye and the severity of the violation so as to allow different step sizes to be used in search for ...
- ArticleMay 2015
Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area
FCCM '15: Proceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing MachinesPages 223–226https://doi.org/10.1109/FCCM.2015.33Integrating reconfigurable fabrics in SOCs require an accurate estimation of the layout area of the reconfigurable fabrics in order to properly accommodate early floor-planning. This work examines the accuracy of using minimum width transistor area, a ...
- articleApril 2014
An improved RC model for VLSI interconnects with applications to buffer insertion
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 79, Issue 1Pages 105–113https://doi.org/10.1007/s10470-013-0135-6A general platform to generate the RC, RLC and RLCG models of interconnects using global approximation method, two-port networks, and asymptotic waveform evaluation (AWE) is presented. Using the delay of transmission-line-modeled interconnects from ...
- articleJuly 2013
A power-efficient 2-dimensional on-chip eye-opening monitor for Gbps serial links
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 76, Issue 1Pages 117–128https://doi.org/10.1007/s10470-013-0083-1This paper investigates the drawbacks of widely used rectangular eye-opening monitors (EOMs) and proposes a new power-efficient half hexagon EOM for Gbps serial links. The proposed EOM outperforms rectangular EOMs by providing a better control of data ...
- articleSeptember 2012
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
Integration, the VLSI Journal (INTG), Volume 45, Issue 4Pages 427–438https://doi.org/10.1016/j.vlsi.2011.11.017Fractional Motion Estimation (FME) is an important part of the H.264/AVC video encoding standard. The algorithm can significantly increase the compression ratio of video encoders while improving video quality. However, it is computationally expensive ...
- articleMay 2012
Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications
Microprocessors & Microsystems (MSYS), Volume 36, Issue 3Pages 151–158https://doi.org/10.1016/j.micpro.2011.12.005Power is a significant design constraint for implementing efficient portable biomedical applications. Operating transistors in the subthreshold region can significantly reduce power consumption; it, however, also reduces performance. While this ...
- articleMay 2012
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs
Microprocessors & Microsystems (MSYS), Volume 36, Issue 3Pages 167–175https://doi.org/10.1016/j.micpro.2011.12.001Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented applications that are designed to process multiple-bit wide data. Studies have shown that the regularity of these multi-bit signals can be ...
- articleMay 2012
A new power-efficient CDMA-based transmitter for high-speed serial links
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 71, Issue 2Pages 343–348https://doi.org/10.1007/s10470-012-9834-7Conventional CDMA serial links suffer from the drawback that the number of transmitters is limited to only two in practical implementations due to the reduced voltage spacing between adjacent logic states of the transmitted data. In this letter, we ...
- research-articleDecember 2011
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Issue 4Article No.: 32, Pages 1–23https://doi.org/10.1145/2068716.2068718The VPR toolset has been widely used in FPGA architecture and CAD research, but has not evolved over the past decade. This article describes and illustrates the use of a new version of the toolset that includes four new features: first, it supports a ...
- research-articleFebruary 2011
The effect of multi-bit correlation on the design of field-programmable gate array routing resources
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 19, Issue 2Pages 283–294https://doi.org/10.1109/TVLSI.2009.2029232As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications. Large arithmetic intensive applications often contain a large proportion of datapath ...
- articleJanuary 2011
A scalable architecture for H.264/AVC variable block size motion estimation on FPGAs
In this paper, we investigate the use of Field-Programmable Gate Arrays (FPGAs) in the design of a highly scalable Variable Block Size Motion Estimation architecture for the H.264/AVC video encoding standard. The scalability of the architecture allows ...
- articleDecember 2010
Effect of serialized routing resources on the implementation area of datapath circuits on FPGAS
In this work, we investigate the effect of serialization on the implementation area of datapath circuits on FPGAs. With ever-increasing logic capacity, FPGAs are being increasingly used to implement large datapath circuits. Since datapath circuits are ...
- research-articleJanuary 2010
Using the minimum set of input combinations to minimize the area of local routing networks in logic clusters containing logically equivalent I/Os in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 18, Issue 1Pages 95–107https://doi.org/10.1109/TVLSI.2008.2008188Mapping digital circuits onto field-programmable gate arrays (FPGAs) usually consists of two steps. First, circuits are mapped into look-up tables (LUTs). Then, LUTs are mapped onto physical resources. The configuration of LUTs is usually determined ...
- research-articleFebruary 2009
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 133–142https://doi.org/10.1145/1508128.1508150The VPR toolset [6, 7] has been widely used to perform FPGA architecture and CAD research, but has not evolved over the past decade to include many architectural features now present in modern FPGAs. This paper describes a new version of the toolset ...