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Computer Science > Hardware Architecture

arXiv:2407.10312 (cs)
[Submitted on 6 May 2024]

Title:Effective Design Verification -- Constrained Random with Python and Cocotb

Authors:Deepak Narayan Gadde, Suruchi Kumari, Aman Kumar
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Abstract:Being the most widely used language across the world due to its simplicity and with 35 keywords (v3.7), Python attracts both hardware and software engineers. Python-based verification environment leverages open-source libraries such as cocotb and cocotb-coverage that enables interfacing the tesbenches with any available simulator and facilitating constrained randomization, coverage respectively. These libraries significantly ease the development of testbenches and have the potential to reduce the setup cost. The goal of this paper is to assess the effectiveness of a Python-Cocotb verification setup with design IPs and compare its features and performance metrics with the current de-facto hardware verification language i.e., SystemVerilog.
Comments: Published in DVCon Europe 2023
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
Cite as: arXiv:2407.10312 [cs.AR]
  (or arXiv:2407.10312v1 [cs.AR] for this version)
  https://doi.org/10.48550/arXiv.2407.10312

Submission history

From: Aman Kumar [view email]
[v1] Mon, 6 May 2024 07:58:16 UTC (599 KB)
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