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Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

El Hafed Boufouss

^*,

Laurent A. Francis

Valeriya Kilchytska

Pierre Gérard

Pascal Simon

and

Denis Flandre

ICTEAM Institute—Electrical Engineering, Université catholique de Louvain, Maxwell Building, Place du Levant 3, B-1348 Louvain-la-Neuve, Belgium

Author to whom correspondence should be addressed.

Sensors 2013, 13(12), 17265-17280; https://doi.org/10.3390/s131217265

Submission received: 7 November 2013 / Revised: 5 December 2013 / Accepted: 9 December 2013 / Published: 13 December 2013

(This article belongs to the Special Issue Sensors for Harsh-Environment Applications)

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Biomedical microsystem adapted from [<a href="#b1-sensors-13-17265" class="html-bibr">1</a>]. ">
Voltage reference circuit adapted from [<a href="#b3-sensors-13-17265" class="html-bibr">3</a>]. ">
Proposed voltage reference circuit. ">
Measured and simulated ID versus VGS curves at 25 °C, VDS = 1.5 V, W = 1 μm, L = 0.28μm. ">
Measured and simulated ID versus VGS curves at 200 °C, VDS = 1.5 V, W = 1 μm, L = 0.28μm. ">
Final layout of the voltage reference. ">
Simulated reference voltage VREF versus temperature and process corners. ">
Measured voltage reference VREFversus temperature. ">
Measured current consumption versus temperature. ">

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Abstract

: This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V_REF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V_REF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm².

Keywords:

biomedical; high temperature; CMOS subthreshold regime; total ionized dose; ultra-low power; voltage reference

1. Introduction

Silicon circuits are increasingly sought by biomedical applications, such as radiation detectors, breathing sensors and temperature sensors. These applications often require ultra-low power circuits, sometimes also robust to harsh environments. Figure 1 shows our previous development [1] of an ultra-low power microsystem, composed of a temperature sensor, a comparator and a voltage reference. This microsystem aims at temperature sensing in the harsh conditions used in medical sterilization such as high total ionized dose radiation (TID) or high temperature. It has three main functions: detecting a user-defined temperature threshold T₀, generating a wake-up signal that turns on a data-acquisition microprocessor above T₀, and measuring temperatures above T₀. The microsystem was developed using a suitable and robust technology, i.e., 1 μm partially-depleted (PD) Silicon-on-Insulator (SOI). Such technology is often used in harsh environments applications because of its attractive features; extended range of working temperature (up to 300 °C), reduced parasitic effects, low-power, high speed and lower sensitivity to transient radiation effects comparing to other technologies [2]. However, during measurements, the voltage reference circuit was the weak point of the microsystem and showed a large shift in the measured reference voltage with radiation of up to 900 mV at 1 Mrad (Si) [3]. To overcome this limitation, a new design of an ultra-low power and harsh-environment immune voltage reference is performed. We firstly choose to port the design to a more suitable SOI industrial technology with Complementary Metal-Oxide-Semiconductor (CMOS) process node of 130 nm featuring a much reduced gate and buried oxides thickness and hence TID degradation [4]. Secondly, we improved the architecture by introducing a cascode bias stage for enhanced stability, and a new start-up design to avoid start deficiency at low temperature and extreme corners (resulting in high V_th). This proposed circuit is optimized to work in the subthreshold regime of the transistors in order to achieve ultra-low power dissipation (less than 100 μW) at high temperature (up to 200 °C).

In this paper, we firstly present the design of the voltage reference circuit. Then, we detail the experimental results of the voltage reference under large range of temperature and under combined high temperature and radiation influence. Lastly, we explain the impact of the combination of high total ionizing dose and high temperature on the proposed circuit and draw conclusions.

2. Basic Concepts

2.1. Voltage Reference Circuit Description

The voltage reference is a CMOS circuit (Figure 2) based on the gate-source voltage difference between a pair of P-type MOS (PMOS) and N-type (NMOS) transistors (M_p and M_n) biased by a proportional to absolute temperature (PTAT) current I_REF (Equation (8)). Differently to the initial work described in [5], our design was: (1) improved by introducing a cascode bias stage for enhanced stability and a new start-up design to avoid start deficiency at extreme temperature and process corners (resulting in high V_th); (2) extended to operate in a large temperature range from −40 to 200 °C; (3) conceived to limit the power dissipation in harsh environments, using transistors optimized to work in subthreshold regime.

In the next paragraph, operation of our previous circuit [3] is reviewed, and in the next sections, an improved architecture is proposed.

2.2. Design Principles

From the analysis of the circuit described in Figure 2, the voltage reference value V_REF and the bias current I_B are obtained as:

V_{REF} = (1 + \frac{R_{1}}{R_{2}}) \cdot V_{GSn} - | V_{GSp} |

(1)

I_{B} = \frac{V_{G S 2} - V_{G S 1}}{R_{B}}

(2)

where V_GSn, V_GSP, V_GS₁ and V_GS₂ are the gate-source voltages for transistors M_n, M_p, M₁ and M₂, respectively. For NMOS and PMOS transistors working in the subthreshold regime, the I – V characteristics can be expressed by [6]:

I_{D n} = β_{n} \cdot U_{T}^{2} \cdot exp (\frac{V_{G S} - V_{thn}}{n \cdot U_{T}}) \cdot [1 - exp (\frac{V_{D S}}{U_{T}})]

(3)

I_{D p} = β_{p} \cdot U_{T}^{2} \cdot exp (\frac{V_{S G} - | V_{thp} |}{n \cdot U_{T}}) \cdot [1 - exp (\frac{V_{S D}}{U_{T}})]

(4)

where β_n = μ_n.C_ox.(W_n/L_n) and β_p = μ_p.C_ox.(W_p/L_p), μ_n,p is the electron and holes mobilities in the channel, C_ox is the oxide capacitance per unit area, V_thn and V_thP are the threshold voltages of NMOS and PMOS respectively, W_n (W_p) and L_n (L_p) are the channel width and length for NMOS (PMOS), respectively. U_T = k_B.T/q is the thermal voltage (k_B is the Boltzmann constant, q the elementary charge and T the absolute temperature), n is the subthreshold slope parameter, V_GS and V_DS (V_SG and V_SD) are the gate-to-source and drain-to-source voltages respectively for the NMOS (PMOS) transistor. For |V_DS| > 4U_T, the drain current I_D becomes almost independent of the drain-to-source voltage [7], so that from Equations (3) and (4) we can extract:

V_{GSn} = n \cdot U_{T} \cdot l n (\frac{I_{D n}}{β_{n} \cdot U_{T}^{2}}) + V_{thn}

(5)

| V_{GSp} | = n \cdot U_{T} \cdot l n (\frac{I_{D p}}{β_{p} \cdot U_{T}^{2}}) + | V_{thp} |

(6)

In Figure 2, if k is the size ratio (W₁.L₂/(L₁.W₂)) of transistors M₁ and M₂, m the current copy ratio in the output stage (I_REF = m.I_B) and using Equations (2) and (5), the bias current I_B is given by:

I_{B} = n \cdot U_{T} \cdot (\frac{l n (k)}{R_{B}})

(7)

I_{REF} = m \cdot n \cdot U_{T} \cdot (\frac{l n (k)}{R_{B}})

(8)

Assuming that the current through the resistances R₁ and R₂ is negligible and using Equations (1), (5) and (6) we obtain the following expression of V_REF:

V_{REF} = n \cdot U_{T} \cdot [ln (\frac{β_{M p}}{β_{M n}}) + M_{r} \cdot ln (\frac{n \cdot m \cdot ln (k)}{R_{B} \cdot β_{M n} \cdot U_{T}})] + (1 + M_{r}) V_{thn} - | V_{thp} |

(9)

with β_Mn₍_p₎ = μ_n₍_p₎.C_ox.(W/L)_n₍_p₎ for the output transistors M_n and M_p respectively (Figure 2). These β parameters (∝T^–^α with α ≥ 1.5) together with the parameter n and the threshold voltage V_thn and V_thp have a temperature dependency [8,9]. M_r is the resistors ratio (R₁/R₂). R_B is a non-silicided polysilicon resistance, showing almost negligible temperature dependency in the simulations.

3. Circuit Realization

A new design of the voltage reference (Figure 3) was developed with a cascoded current source, to reduce the V_REF variations due to the process corners, supply voltage variation and mainly the radiation effects caused by single ionized particles [10]. As it is based on the same principle as the previous design [3], the voltage reference expression V_REF remains unchanged (Equation (9)).

3.1. Design Phases

3.1.1. Technology Characterization at High Temperature

The voltage reference circuit was developed based on the analog MOSFETs of an industrial 130 nm PD SOI CMOS featuring a 5 nm gate oxide thickness and 280 nm minimum length. The SPICE (BSIM3SOI) models available for this technology are commercially validated up to 150 °C. We checked the models validity up to 200°C, by comparing the typical DC I_D(V_GS) characteristic of a MOSFET transistor extracted by simulations and from measurements for different temperatures (25, 150, 175 and 200 °C). Figures 4 and 5 show two examples of the good agreement between simulated and measured curves, for NMOS and PMOS transistors at 25 °C and 200 °C, in the subthreshold region of interest. The slight discrepancies for the PMOS transistor can be neglected since the circuit design has to cope with much larger variations due to process, temperature and radiations.

3.1.2. Design Optimization

The design optimization consists in determining the bias current I_B and the transistor and resistor sizes (in Figure 3) to minimize the V_REF variation with the device physical parameters as given by the previous equations and process corners. The temperature dependence of the voltage reference must be as low as possible. The aforesaid dependence is expressed by evaluating the temperature coefficient (TC) defined by the following expression:

[T C] = \frac{1}{V_{REF}} \times [\frac{d V_{REF}}{d T}]

(10)

In order to minimize the TC coefficient for our design, we have extracted temperature dependencies of the physical parameters, computed Equation (10) and searched the best design parameters (W₁, W₂, L_n, m, M_r, W_n, W_p and R_B). However this first guess does not take into account the process corners. Next, extensive ELDO (Mentor Graphics) simulations were performed for the different process corners in a temperature range of −40 to 200 °C.

3.2. Design Robustness Against Radiation Effects

To take into account the variations due to radiation effects, additional constraints were considered as follow:

The designed circuit was checked with custom model parameters of transistors including TID effects on transistors [11] (up to 30% mobilities degradation and negative voltage threshold shifts of 100 mV).
Using transistors with a body contact to limit the effect of the parasitic bipolar possibly created by radiation [10].
Choosing relatively long transistor to assure lower leakage current and lower threshold voltages shift, which may appear as a result of TID and high-temperature effects [2,12,13].
The circuit layout is further carried out by paying attention to critical components; thus all matched device pairs were realized by a centroid implementation, including the necessary dummies (Figure 6).

Table 1 gives the bias setting and different dimensions of transistors and resistors used in the proposed voltage reference circuit.

3.3. Simulations Results

Simulations are performed for five different process corners and a custom model parameters of transistors including TID effects, namely:

Typ: typical corner (typical |V_th| values)
FFA: Fast PMOS and NMOS (min |V_th| values) with minimum resistances values
SSA: Slow PMOS and NMOS (max |V_th| with maximum resistances values
FSA and SFA: are the crossed cases (fast and slow)
RAD: Custom model parameters of transistors including TID effects (30% degradation of the mobility and a threshold voltage shift of 100 mV).

As shown in Figure 7, the reference voltage V_REF versus temperature range of −40 to 200 °C gives an average voltage of 1.5 V for Typical corner, with a variation of ±8% over all process corners and temperature/radiation conditions. More specifically, lower |V_th| values lead to a lower V_REF at a given temperature according to Equation (9), whereas the temperature dependence depends on the exact balance between the n, U_T and the V_th terms.

4. Experimental Results

The main purpose of our voltage reference is to be used in a harsh biomedical sterilization conditions. To validate this feature, first the voltage reference circuit was measured in a large range of temperatures from −40 to 200 °C. Subsequently, other chips have been tested during irradiation at different temperatures, using a small ceramic heater resistor placed under chips. Irradiation was performed at the Cyclotron facility of UCL with Gamma-rays, using a Cobalt source (⁶⁰Co). The next sections present the measured results for a power supply of 2.5 V.

4.1. Temperature Measurements

The experimental voltage reference generates a mean reference voltage of about 1.5 V (Figure 8) with a variation of about 1%, for the temperature range of −40–90 °C with a temperature coefficient less than 133 ppm/ °C. This increases to 470 ppm/ °C for the large tested temperature range of −40–200 °C with a maximum variation of 10%. The maximum power dissipation is less than 42 μW at the lower temperature of −40 °C, about 50 μW at room temperature and only 75 μW at a high temperature of 200 °C (Figure 9).

The 10% increase of the reference voltage value V_REF textitversus temperature can be explained through the increase of the subthreshold current and parameters n, U_T and (1/β_Mn) shown in the Equation (9). The decrease of the absolute values of threshold voltages of transistors V_thn and |V_thp| with temperature [8] helps (but not sufficiently) to limit the increase of V_REF value versus temperature. To first order, the power dissipation of the circuit is equal to “V_DD.(m+2).I_B” and according to Equation (8) is proportional to the term n.U_T (∝ n.T). This explains the linear variation with temperature of the power dissipation of the reference voltage (Figure 9).

4.2. Measurements under Combined High Temperature and Radiation Exposure

Six chips were exposed to gamma-rays radiation during one week with a dose rate of 10 krad/h and regularly measured. Two chips were kept at room temperature, two heated at 100 °C during radiation and the last two chips at 200 °C. The voltage reference value remains about the expected voltage of 1.5 V with a maximum increase of ±5% shift for room and 200 °C temperature. At 100 °C the voltage reference value increases with total dose up to 400 krad (Si) and starts to decrease at higher dose (Figure 10). The power consumption of the voltage reference increases with radiation and temperature, except for the highest heating temperature during radiation for which the power remains stable at about 75 μW upon radiation (Figure 11). Similar trends are observed for all measured chips. Similarly to temperature case, we can express the radiation dependencies of the voltage reference circuit. This is about 25 ppm/krad for room temperature up to 1 Mrad (Si).

4.3. Discussion of Measurement Results

In order to understand the effect of the combination of radiation and high temperature on the designed voltage reference circuit, the threshold voltages Vth_n,p for the used SOI transistors were extracted in the same conditions (irradiation + temperatures). Gamma-rays radiation is known to result in oxide and interface charges build-up (N_ox and N_it). They shift the threshold voltages as (Vth_n ∝ (N_it – N_ox) and |Vth_p| ∝ (N_it + N_ox)) and degrade mobilities in transistors [11].

Thus, for PMOS (Figure 12) the absolute |Vth_p| value increases with radiation. This effect is amplified at 200 °C due to higher N_it creation. For NMOS transistor (Figure 13), at room temperature, induced N_ox charges are dominant (versus N_it) and, therefore Vth_n value decreases slightly. At 100 °C a balance between N_ox and N_it occurs and keeps a relatively stable value for Vth_n versus radiation dose. N_it becomes dominant at 200 °C and leads to an increase of the NMOS threshold voltage with dose.

Then, based on the previous expression of V_REF (Equation (9)) and knowing that the parameter n is increased and the carrier mobilities μ_n₍_p₎ are degraded both by radiation and temperature [11,14], we can explain the combined effect of radiation and temperature on the circuit (Figures 10 and 11) as follows.

At room temperature: As the shift of threshold voltages of PMOS and NMOS seems to be small, the increase of V_REF and the power dissipation can be explained by the increase of the parameter n and the decrease of the mobility μ_n (∝ to 1/β_Mn) under radiation.
At 100 °C: At small dose (less than 400 krad) the same effects as for room temperature occur. For higher dose, the absolute value of the threshold voltage of PMOS increases while the NMOS one remains quasi stable, thus leading to the decrease of the voltage value of V_REF and to stabilize the power dissipation.
At 200 °C: After an initial decrease of Vth_n and increase of |Vth_p| which is reflected in a decrease of V_REF and the power dissipation, both absolute values of Vth_n and Vth_p increase under radiation. Thus, they compensate each other in the Equation (9) leading to a stable value of V_REF and power consumption.

4.4. Comparison with the State of the Art

Table 2 summarizes the performance of the proposed voltage reference circuit and compares it with results of the literature. When compared to our previous work [3], the new circuit is twice less sensitive to temperature variation and the sensitivity to radiation is divided by more than one order of magnitude thanks to: (1) the suitable SOI technology featuring a reduced oxide thickness (5 nm in this work versus 25 nm in the previous work) which limits oxide charge build-up and hence TID degradation; (2) to the new design circuit performed with reasonable margin for the current consumption.

When compared to literature, the proposed circuit operates in a wider range of temperature −40 to 200 °C and radiation (up to 1 Mrad (Si)) than other solutions. Our circuit proposes a high reference voltage value of 1.5 V with a small current consumption (less than 20 μA at room temperature) and achieves a low temperature coefficient for a similar range of temperature.

5. Conclusions

In this work we demonstrated an ultra-low power voltage reference circuit, designed in the subthreshold regime of transistors, developed to be used in harsh environment such as biomedical sterilization. This circuit was simulated up to 200 °C using our extended MOS models and was shown to consume about 75 μW only at higher temperature. The design was verified to be robust against radiation effects (using custom model parameters) and the voltage reference value very fairly stable over a large range of process corners and temperature variations. To enhance immunity to total dose effects, the layout has been implemented using specific guidelines and a suitable SOI CMOS technology with thin gate and buried oxides. Measurements have shown a fairly correct operation of such ultra-low power circuit for a large temperature range (from −40 °C up to 200 °C) and under a combination of total ionizing dose (up to 1 Mrad (Si)) and high temperature. The threshold voltages Vth_n,p for the used SOI transistors were extracted under radiation and temperature. They show a significant increase of the absolute value of PMOS threshold voltage with radiation at high temperature, while for NMOS the threshold voltage value Vth_n decreases slightly at room temperature, keeps a relative stable value versus radiation dose at 100 °C and increases at higher temperature 200 °C, depending on the balance between N_ox and N_it build-up. The results fairly support the observed V_REF and power consumption dependences on temperature and total dose radiation.

Acknowledgments

This work is supported by the Région wallonne (Skywin Projects S@T and Telecom), and the F.R.S.-FNRS of Belgium. The authors would like to thank UCL Cyclotron facility and D. Spôte for his assistance with temperature setup.

Conflict of Interest

The authors declare no conflict of interest.

References

Assaad, M.; Boufouss, E.; Gérard, P.; Francis, L.; Flandre, D. Design and characterization of ultra-low power SOI-CMOS IC temperature level detector. Electron. Lett. 2012, 48, 842–844. [Google Scholar]
Colinge, J.-P. Silicon-on-Insulator Technology: Materials to VLSI, 2nd ed.; Kluwer Academic Publishers: Boston, MA, USA, 1997; pp. 223–237. [Google Scholar]
Assaad, M.; Boufouss, E.; Gérard, P.; Francis, L.; Flandre, D. Ultra Low Power CMOS Circuits Working in Subthreshold Regime for High Temperature and Radiation Environments. Proceedings of the International Conference and Exhibition on High Temperature Electronics Network, Oxford, UK, 18–20 July 2011.
Dumitru, R.; Hafer, C.; Wu, T.W.; Rominger, R.; Gardner, H.; Milliken, P.; Bruno, K.; Farris, T. Radiation Hardness Characterization of a 130 nm Technology. Proceedings of the IEEE Radiation Effects Data Workshop, Honolulu, HI, USA, 23–27 July 2007; pp. 123–130.
Ka, N.L.; Mok, P.K.T. A CMOS Voltage Reference Based on Weighted Difference of Gate-Source Voltage between PMOS and NMOS Transistors for Low Dropout Regulators. Proceedings of the 27th European Solid-State Circuits Conference, Villach, Austria, 18–20 September 2001; pp. 61–64.
Behazd, R. Design of Analog CMOS Integrated Circuit, 1st ed.; McGraw-Hill: New York, NY, USA, 2000; pp. 27–28. [Google Scholar]
Shihabudheen, T.; Babu, VS.; Baiju, M.R. A Low Power Sub 1V 3.5-ppm/C Voltage Reference Featuring Subthreshold MOSFETs. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, St. Julien's, Malta, 31 August–3 September 2008; pp. 442–445.
Filanovsky, I.M.; Allam, A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans. Circ. Syst. I: Fundament. Theory Appl. 2001, 48, 876–884. [Google Scholar]
Rudenko, T.; Kilchytska, V.; Colinge, J.; Dessard, V.; Flandre, D. On the high-temperature subthreshold slope of thin-film SOI MOSFETs. IEEE Electr. Dev. Lett. 2002, 23, 148–150. [Google Scholar]
Boufouss, E.; Alvarado, J.; Flandre, D. Compact Modeling of the High Temperature Effect on the Single Event Transient Current Generated by Heavy Ions in SOI 6T-SRAM. Proceedings of the International Conference on High Temperature Electronics, Albuquerque, NM, USA, 11–13 May 2010.
Alvarado, J.; Boufouss, E.; Kilchytska, V.; Flandre, D. Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs. Microelectr. Reliab. 2010, 50, 1852–1856. [Google Scholar]
Kilchytska, V.; Alvarado, J.; Collaert, N.; Rooyakers, R.; Militaru, O.; Berger, G.; Flandre, D. Effect of high-energy neutrons on MuGFETs. Solid-State Electr. 2009, 54, 196–204. [Google Scholar]
Barnaby, H.J. Total-ionizing-dose effects in modern CMOS technologies. IEEE Trans. Nuclear Sci. 2006, 55, 3103–3121. [Google Scholar]
Holmes-Siedle, A.; Adams, L. Handbook of Radiation Effects, 2nd ed.; Oxford University Press: London, UK, 2007; pp. 162–163. [Google Scholar]
Malcovati, P.; Maloberti, F.; Pruzzi, M.; Fiocchi, C. Curvature-compensated BiCMOS bandgap with 1-V supply voltage. Solid-State Circuit IEEE 2001, 36, 1076–1081. [Google Scholar]
Ivanovich, S.E.; Ivanovich, G.A. Voltage References Based on Radiation Hardened Analogous Matrix Master Dice. Proceedings of the International Conference on Signals and Electronic Systems, Gliwice, Poland, 7–10 September 2010; pp. 265–268.
Gromov, V.; Annema, A.J.; Kluit, R.; Visschers, J.L.; Timmer, P. A radiation hard bandgap reference circuit in a standard 0.13 μm CMOS technology. IEEE Trans. Nuclear Sci. 2007, 54, 2727–2733. [Google Scholar]

Figure 1. Biomedical microsystem adapted from [1].

Figure 2. Voltage reference circuit adapted from [3].

Figure 3. Proposed voltage reference circuit.

Figure 4. Measured and simulated I_D versus V_GS curves at 25 °C, V_DS = 1.5 V, W = 1 μm, L = 0.28μm.

Figure 5. Measured and simulated I_D versus V_GS curves at 200 °C, V_DS = 1.5 V, W = 1 μm, L = 0.28μm.

Figure 6. Final layout of the voltage reference.

Figure 7. Simulated reference voltage V_REF versus temperature and process corners.

Figure 8. Measured voltage reference V_REFversus temperature.

Figure 9. Measured current consumption versus temperature.

Figure 10. Measured voltage reference V_REFvs TID at different temperatures.

Figure 11. Measured voltage reference power consumption at 2.5 V power supply, in the same conditions as in Figure 10.

Figure 12. Measured PMOS voltage threshold vs TID at different temperatures.

Figure 13. Measured NMOS voltage threshold vs TID at different temperatures.

Table 1. Voltage references bias setting and devices dimensions.

**Table 1.** Voltage references bias setting and devices dimensions.
Parameter	Description	Value
VDD	Power supply	2.5 V
I_B	Bias current @ 25 °C	2.5μA
(W/L)_l	Size of NMOS M₁	40 μm/0.5 μm
(W/L)₂	Size of NMOS M₂	10 μm/0.5 μm
(W/L)_3–6	Size of PMOS M₃,M₄,M₅ and M₆	10 μm /0.5 μm
(W/L)_7–8	Size of PMOS M₇ and M₈	25 μm/0.5 μm
(W/L)_p	Size of PMOS M_p	200 μm/0.5 μm
(W/L)_n	Size of NMOS M_n	20 μm/1 μm
(W/L)₉	Size of NMOS M₉	5 μm/0.5 μm
(W/L)_st	Size of NMOS M_st	5 μm/1 μm
R_B	R_B resistor value	25 kΩ
R₁	R₁ resistor value	50 MΩ
R₂	R₂ resistor value	20 MΩ
R_st	R_st resistor value	1.5 MΩ

Table 2. Performance comparison with similar voltage references described in the literature.

**Table 2.** Performance comparison with similar voltage references described in the literature.
Parameter	This Work	Previous work [3]	Leung [5]	Malcovati [15]	Ivanovic [16]	Gromov [17]
Technology	0.13 μm SOI	1 μm SOI	0.6 μm Bulk	0.35 μm BiCMOS	–	0.13 μm Bulk
Supply voltage	2.5 V	5 V	1.4 to 3 V	1 V	–	1.4 V
Reference voltage (V)	1.5	1.8	0.333	0.54	1.6	0.405
Temperature range (°C)	–40–200 133 [–40, 90 °C]	–40–300 375 [–40, 90 °C]	0–100	0–80	–40–120	0–80
TC(ppm/°C)	470 [–40, 200 °C]	825 [–40, 200 °C]	94	212	90	200
Consumption @ 25 °C	20 μA	2 μA	9.7μA	92 μA	–	–
V_REF shift due to radiation (ppm/krad)	25	426	–	–	140	0.68
Irradiation particles	Gamma-rays	Gamma-rays	–	–	Neutron	X-rays
Maximum V_REF shift due to Combined effect of temperature and radiation up to 1 Mrad (Si)	+10%	–	–	–	–	–
Dose Mrad (Si)	1	1	–	–	1	44

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Boufouss, E.H.; Francis, L.A.; Kilchytska, V.; Gérard, P.; Simon, P.; Flandre, D. Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference. Sensors 2013, 13, 17265-17280. https://doi.org/10.3390/s131217265

AMA Style

Boufouss EH, Francis LA, Kilchytska V, Gérard P, Simon P, Flandre D. Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference. Sensors. 2013; 13(12):17265-17280. https://doi.org/10.3390/s131217265

Chicago/Turabian Style

Boufouss, El Hafed, Laurent A. Francis, Valeriya Kilchytska, Pierre Gérard, Pascal Simon, and Denis Flandre. 2013. "Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference" Sensors 13, no. 12: 17265-17280. https://doi.org/10.3390/s131217265

APA Style

Boufouss, E. H., Francis, L. A., Kilchytska, V., Gérard, P., Simon, P., & Flandre, D. (2013). Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference. Sensors, 13(12), 17265-17280. https://doi.org/10.3390/s131217265

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