Article

Optimal gate sizing for coupling-noise reduction

Authors:

Debjit Sinha,

Hai Zhou,

Chris C. N. ChuAuthors Info & Claims

ISPD '04: Proceedings of the 2004 international symposium on Physical design

Pages 176 - 181

https://doi.org/10.1145/981066.981104

Published: 18 April 2004 Publication History

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Abstract

Coupling-noise reduction has emerged as a critical design problem with VLSI feature sizes shrinking rapidly and with the use of more aggressive and less noise-immune circuits. Since coupling-noise on a net depends on driving gate-sizes of the net itself and all nets coupled to it, gate-sizing emerges as an effective approach to coupling-noise reduction. It is an attractive approach since re-routing is not required. In this paper, we propose an iterative gate-sizing algorithm to determine optimal gate-sizes for coupling-noise reduction. We consider gate-sizing as a fixpoint computation on a complete lattice and the beauty of the iterative gate-sizing algorithm lies in its ability to guarantee the optimal solution, provided it exists. The effectiveness of the algorithm is validated experimentally by simulations on multiple large circuits.

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Cited By

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Fan FChen HLiu ILin Y(2010)Technology mapping with crosstalk noise avoidanceProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899790(319-324)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899790
Fang-Yu Fan Chen HI-Min Liu (2010)Technology mapping with crosstalk noise avoidance2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419876(319-324)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419876
Sinha DZhou H(2006)Gate-size optimization under timing constraints for coupling-noise reductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85593225:6(1064-1074)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.855932
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Optimal gate sizing for coupling-noise reduction

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Information

Published In

ISPD '04: Proceedings of the 2004 international symposium on Physical design

April 2004

226 pages

ISBN:1581138172

DOI:10.1145/981066

General Chair:
Charles J. Alpert,
IBM
,
Program Chair:
Patrick Groeneveld
Eindhoven University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 April 2004

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April 18 - 21, 2004

Arizona, Phoenix, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

View all

Fan FChen HLiu ILin Y(2010)Technology mapping with crosstalk noise avoidanceProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899790(319-324)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899790
Fang-Yu Fan Chen HI-Min Liu (2010)Technology mapping with crosstalk noise avoidance2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419876(319-324)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419876
Sinha DZhou H(2006)Gate-size optimization under timing constraints for coupling-noise reductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85593225:6(1064-1074)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.855932
Sinha DZhou HTang T(2005)Yield driven gate sizing for coupling-noise reduction under uncertaintyProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120803(192-197)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120803
Sinha DHai Zhou (2005)Yield driven gate sizing for coupling-noise reduction under uncertaintyProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466156(192-197)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466156
Sinha DZhou H(2004)Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxationProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382535(14-19)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382535

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Gate-size optimization under timing constraints for coupling-noise reduction

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