[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/968280.968316acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
Article

An FPGA implementation of block truncation coding for gray and color images

Published: 22 February 2004 Publication History

Abstract

This paper presents an FPGA implementation for the Block Truncation Coding (BTC) image compression technique. Images are divided into equal blocks. The BTC calculates the mean of each block for which a two-level quantization is performed so that a zero value is stored for the pixels with values smaller than the mean. The rest of the pixels are represented by the value one. The implementation exploits the inherent parallelism of the algorithm to provide efficient algorithm-to-architecture mapping. FPGA implementation of the BTC is composed of three modules: the input module, to receive input pixels; the quantizer module, to classify pixels to one of the two levels;= and divider circuits to obtain the two quantized values. The implementation is performed for gray and color images. The Xilinx-VirtexE BTC implementation has shown to provide about 23.4x10 6 of pixels/second processing rate which is about 3500 times faster than an Intel Pentium III-550-MHz processor.
  1. An FPGA implementation of block truncation coding for gray and color images

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
    February 2004
    266 pages
    ISBN:1581138296
    DOI:10.1145/968280
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 22 February 2004

    Permissions

    Request permissions for this article.

    Check for updates

    Qualifiers

    • Article

    Conference

    FPGA04
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 125 of 627 submissions, 20%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • 0
      Total Citations
    • 0
      Total Downloads
    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 01 Jan 2025

    Other Metrics

    Citations

    View Options

    View options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media