Article

A semi-custom voltage-island technique and its application to high-speed serial links

Authors:

Juan-Antonio Carballo,

Jeffrey L. Burns,

Seung-Moon Yoo,

Ivan Vo,

V. Robert NormanAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

Pages 60 - 65

https://doi.org/10.1145/871506.871525

Published: 25 August 2003 Publication History

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Abstract

Supply-voltage reduction is a known technique for reducing CMOS active power. We propose a semi-custom voltage-island approach based on internal regulation and selective custom design. This approach enables transparent embedding, since no additional external power supply is needed. We apply the approach to high-speed serial links, and we show that high performance is retained through targeted application of custom circuit and logic design. A chip is presented that evaluates the presented approach on a 3000-gate 3.2-Gbps multi-protocol serial-link receiver logic core. When reducing the supply from 1.2V to 0.95V, the chip demonstrates power savings of over 25%.

References

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Biondi ANatale MButtazzo GPazzaglia P(2018)Selecting the Transition Speeds of Engine Control Tasks to Optimize the PerformanceACM Transactions on Cyber-Physical Systems10.1145/31270222:1(1-26)Online publication date: 3-Jan-2018
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Index Terms

A semi-custom voltage-island technique and its application to high-speed serial links
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Information

Published In

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

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ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Biondi ANatale MButtazzo GPazzaglia P(2018)Selecting the Transition Speeds of Engine Control Tasks to Optimize the PerformanceACM Transactions on Cyber-Physical Systems10.1145/31270222:1(1-26)Online publication date: 3-Jan-2018
https://dl.acm.org/doi/10.1145/3127022
Ali UEgerstedt M(2018)Hybrid Optimal Control under Mode Switching Constraints with Applications to Pesticide SchedulingACM Transactions on Cyber-Physical Systems10.1145/30474112:1(1-17)Online publication date: 3-Jan-2018
https://dl.acm.org/doi/10.1145/3047411
Zhang YLiu ZMiao ZWu WLiu KSun Z(2015)Singe image-based data-driven indoor scenes modelingComputers and Graphics10.1016/j.cag.2015.10.00453:PB(210-223)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1016/j.cag.2015.10.004
Russell IMarkov ZNeller TColeman S(2010)MLeXAIACM Transactions on Computing Education10.1145/1821996.182199910:3(1-36)Online publication date: 1-Aug-2010
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Chang LDu C(2009)Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollersACM Transactions on Design Automation of Electronic Systems10.1145/1640457.164046315:1(1-36)Online publication date: 28-Dec-2009
https://dl.acm.org/doi/10.1145/1640457.1640463
Rao RJoshi VBlaauw DSylvester D(2009)Circuit optimization techniques to mitigate the effects of soft errors in combinational logicACM Transactions on Design Automation of Electronic Systems10.1145/1640457.164046215:1(1-27)Online publication date: 28-Dec-2009
https://dl.acm.org/doi/10.1145/1640457.1640462
Wu MLu MChen HJou J(2009)Performance-constrained voltage assignment in multiple supply voltage SoC floorplanningACM Transactions on Design Automation of Electronic Systems10.1145/1640457.164046015:1(1-17)Online publication date: 28-Dec-2009
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Armoni MBen-Ari M(2009)The concept of nondeterminismACM SIGCSE Bulletin10.1145/1595453.159549541:2(141-160)Online publication date: 25-Jun-2009
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Ha PTsigas PAnshus O(2009)Non-blocking programming on multi-core graphics processorsACM SIGARCH Computer Architecture News10.1145/1556444.155644836:5(19-28)Online publication date: 20-Jun-2009
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Lu MWu MChen HJiang H(2006)Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design2006 IEEE International SOC Conference10.1109/SOCC.2006.283883(211-214)Online publication date: Oct-2006
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Abstract

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Cited By

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Recommendations

Postplacement Voltage Island Generation

Low power noise immune node voltage comparison keeper design for high speed architectures

Voltage-Island partitioning and floorplanning under timing constraints

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