Article

Free access

The Tera computer system

Authors:

Burton SmithAuthors Info & Claims

ICS '90: Proceedings of the 4th international conference on Supercomputing

Pages 1 - 6

https://doi.org/10.1145/77726.255132

Published: 01 June 1990 Publication History

PDF eReader

References

[1]

T. J. Dekker. A floating-point technique for extending the available precision. Numerische Math., 18:224-242, 1971.

Digital Library

Google Scholar

[2]

M. Flynn. Some computer organizations and their effectiveness. IEEE Transactions on Computers, C-21(9):948-960, September 1972.

Digital Library

Google Scholar

[3]

A. Gottlieb, R,. Grishman, C. P. Kruskal, K. P. McAuliffe, L. Rudolph, and M. Snir. The NYU Ultracomputer - designing an MIMD shared memory parallel computer. IEEE Transactions on Computers, C-32(2):175-189, 1984.

Google Scholar

[4]

W. Kahan. Doubled-precision IEEE standard 754 floating-point arithmetic. Unpublished manuscript, February 1987.

Google Scholar

[5]

R. M. Keller. Rediflow: A proposed architecture for combining reduction & dataflow. In PAW83: Visuals Used at the 1983 Parallel Architecture Workshop, University of Colorado, Boulder, 1983.

Google Scholar

[6]

J. T. Kuehn and B. J. Smith. The Horizon supercomputer system: Architecture and software. In Proceedings of Supercomputing '88, Orlando, Florida, November 1988.

Digital Library

Google Scholar

[7]

S. Linnainmaa. Software for doubled-precision floating-point computations. A CM Transactions on Mathematical Software, 7:272-283, 1981.

Digital Library

Google Scholar

[8]

A. Norton and E. Melton. A class of boolean linear transformations for conflict-free power-of-two stride access. In Proceedings of the 1987 International Conference on ParaUel Processing, pages 247-254, August 1987.

Google Scholar

[9]

Frank Pittelli and David Smitley. Analysis of a 3d toriodal network for a,fihared memory architecture. In Proceedings of S'upercomputing '88, Orlando, Florida, November 1(,)88.

Digital Library

Google Scholar

[10]

M. R. Thistle and B. J. Smith. A processor architecture for Horizon. In Proceedings of Supercomputing '88, pages 35-41, Orlando, Florida, November 1988.

Digital Library

Google Scholar

Cited By

View all

Rajasukumar AZhang TXu RChien A(2024)UpDown: A Novel Architecture for Unlimited Memory ParallelismProceedings of the International Symposium on Memory Systems10.1145/3695794.3695801(61-77)Online publication date: 30-Sep-2024
https://dl.acm.org/doi/10.1145/3695794.3695801
Li BXiang ZWang XRuan HZhou JTan K(2023)FastWake: Revisiting Host Network Stack for Interrupt-mode RDMAProceedings of the 7th Asia-Pacific Workshop on Networking10.1145/3600061.3600063(1-7)Online publication date: 29-Jun-2023
https://dl.acm.org/doi/10.1145/3600061.3600063
Neff RMinutoli MTumeo ABecchi MBartolini ARietveld KSchuman CMoreira J(2023)High-Level Synthesis of Irregular ApplicationsProceedings of the 20th ACM International Conference on Computing Frontiers10.1145/3587135.3592196(12-22)Online publication date: 9-May-2023
https://dl.acm.org/doi/10.1145/3587135.3592196
Show More Cited By

Index Terms

The Tera computer system

Recommendations

Multi-processor performance on the Tera MTA
SC '98: Proceedings of the 1998 ACM/IEEE conference on Supercomputing

The Tera MTA is a revolutionary commercial computer based on a multithreaded processor architecture. In contrast to many other parallel architectures, the Tera MTA can effectively use high amounts of parallelism on a single processor. By running ...
An initial evaluation of the Tera Multithreaded Architecture and programming system using the C3I parallel benchmark suite
SC '98: Proceedings of the 1998 ACM/IEEE conference on Supercomputing

The Tera Multithreaded Architecture (MTA) is a radical new architecture intended to revolutionize high-performance computing in both the scientific and commercial marketplaces. Each processor supports 128 threads in hardware. Extremely fast thread ...
Performance analysis and portability issues of 64-bit message passing interface for Tera scale system
SEPADS'07: Proceedings of the 6th WSEAS International Conference on Software Engineering, Parallel and Distributed Systems

This paper describes the issues underlying the development of 64-bit C-MPI (C-DAC Message Passing Interface) and the porting semantic and strategies of 64-bit C-MPI. This work discusses various issues arising during the porting from 32-bit C-MPI to 64-...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICS '90: Proceedings of the 4th international conference on Supercomputing

June 1990

492 pages

ISBN:0897913698

DOI:10.1145/77726

Chairmen:
Ahmed Sameh
Univ. of Illinois
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands

ACM SIGARCH Computer Architecture News Volume 18, Issue 3b
Special Issue: Proceedings of the 4th international conference on Supercomputing
Sept. 1990
489 pages
ISSN:0163-5964
DOI:10.1145/255129
Chairmen:
Ahmed Sameh
Univ. of Illinois at Urbana-Champaign, Urbana
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands
Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1990

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

IC'90

Sponsor:

SIGARCH

IC'90: ACM SIGARCH International Conference on Supercomputing

June 11 - 15, 1990

Amsterdam, The Netherlands

Acceptance Rates

Overall Acceptance Rate 629 of 2,180 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

636
Total Citations
View Citations
4,594
Total Downloads

Downloads (Last 12 months)1,218
Downloads (Last 6 weeks)128

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Rajasukumar AZhang TXu RChien A(2024)UpDown: A Novel Architecture for Unlimited Memory ParallelismProceedings of the International Symposium on Memory Systems10.1145/3695794.3695801(61-77)Online publication date: 30-Sep-2024
https://dl.acm.org/doi/10.1145/3695794.3695801
Li BXiang ZWang XRuan HZhou JTan K(2023)FastWake: Revisiting Host Network Stack for Interrupt-mode RDMAProceedings of the 7th Asia-Pacific Workshop on Networking10.1145/3600061.3600063(1-7)Online publication date: 29-Jun-2023
https://dl.acm.org/doi/10.1145/3600061.3600063
Neff RMinutoli MTumeo ABecchi MBartolini ARietveld KSchuman CMoreira J(2023)High-Level Synthesis of Irregular ApplicationsProceedings of the 20th ACM International Conference on Computing Frontiers10.1145/3587135.3592196(12-22)Online publication date: 9-May-2023
https://dl.acm.org/doi/10.1145/3587135.3592196
Giannoula CVijaykumar NPapadopoulou NKarakostas VFernandez IGomez-Luna JOrosa LKoziris NGoumas GMutlu O(2021)SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00031(263-276)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00031
Dutu ASinclair MBeckmann BWood DChow M(2020)Independent Forward Progress of Work-groups2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA45697.2020.00087(1022-1035)Online publication date: May-2020
https://doi.org/10.1109/ISCA45697.2020.00087
Fan WHe JHan ZLi PWang R(2020) Reconfigurable Fault‐tolerance mapping of ternary N ‐cubes onto chips Concurrency and Computation: Practice and Experience10.1002/cpe.565932:11Online publication date: 7-Jan-2020
https://doi.org/10.1002/cpe.5659
Budhkar PAbsalyamov IZois VWindh SNajjar WTsotras V(2019)Accelerating In-Memory Database Selections Using Latency Masking Hardware ThreadsACM Transactions on Architecture and Code Optimization10.1145/331022916:2(1-28)Online publication date: 9-Apr-2019
https://dl.acm.org/doi/10.1145/3310229
Bijlsma TBekooij MSmit G(2019)Circular Buffers with Multiple Overlapping Windows for Cyclic Task GraphsTransactions on High-Performance Embedded Architectures and Compilers V10.1007/978-3-662-58834-5_3(39-58)Online publication date: 23-Feb-2019
https://doi.org/10.1007/978-3-662-58834-5_3
Aamodt TFung WRogers T(2018)General-Purpose Graphics Processor ArchitecturesSynthesis Lectures on Computer Architecture10.2200/S00848ED1V01Y201804CAC04413:2(1-140)Online publication date: 21-May-2018
https://doi.org/10.2200/S00848ED1V01Y201804CAC044
Zhang DMa XThomson MChiou D(2018)MinnowACM SIGPLAN Notices10.1145/3296957.317319753:2(593-607)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173197
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Multi-processor performance on the Tera MTA

An initial evaluation of the Tera Multithreaded Architecture and programming system using the C3I parallel benchmark suite

Performance analysis and portability issues of 64-bit message passing interface for Tera scale system