Article

Buffer sizing for minimum energy-delay product by using an approximating polynomial

Authors:

Chang Woo Kang,

Soroush Abbaspour,

Massoud PedramAuthors Info & Claims

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

Pages 112 - 115

https://doi.org/10.1145/764808.764838

Published: 28 April 2003 Publication History

Get Access

Abstract

This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next, the paper describes a sizing method for tapered buffer chains. It is shown that the first-order sizing behavior, which considers only the capacitive energy dissipation, can be improved by considering the short-circuit dissipation as well, and that the second-order polynomial expressions for short-circuit energy improves the accuracy over linear expressions. These results are used to derive sizing rules for buffered chains, which optimize the overall energy-delay product.

References

[1]

H. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE J. Solid-State Circuits, vol. SC-19, pp. 468--473, 1984.

Crossref

Google Scholar

[2]

T. Sakurai, A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter and other formulas," IEEE J. Solid-State Circuits, vol. 25, pp. 584--594, April 1990.

Crossref

Google Scholar

[3]

S. Nikolaidis and A. Chatzigeorgiou, "Modeling the transistor chain operation in CMOS gates for short channel devices," IEEE Transactions on Circuits and Systems, vol. 46, no. 10, October 1999.

Google Scholar

[4]

P. Maurine, M. Rezzoug and D. Auvergne, "Output transition time modeling of CMOS structures", IEEE International Symposium on Circuits and Systems, vol. 5, pp. 363--366, 2001.

Google Scholar

[5]

A. Chatzigeorgiou and S. Nikolaidis, "Collapsing the CMOS transistor chain to an effective single equivalent transistor," in IEE Proc. on Circuits, Devices and Systems, vol. 145, no. 5, pp. 347--353, October 1998.

Crossref

Google Scholar

[6]

U. Ko and P. T. Balsara, "Short-circuit power driven gate sizing technique for reducing power dissipation," IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 3, September 1995.

Digital Library

Google Scholar

[7]

S. Turgis, N. Azemard, and D. Auvergne, "Explicit evaluation of short-circuit power dissipation and its influence on propagating delay for static CMOS gates," in Proc. IEEE Int. Symp.on Circuits and Systems, vol. 4, pp. 751--754, May 1996.

Google Scholar

[8]

M. Borah, R. Michael Owens, and M. J. Irwin, "Transistor sizing for low power CMOS circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no.6, June 1996.

Digital Library

Google Scholar

[9]

L. Bisdounis, O. Koufopavlou, and S. Nikolaidis, "Accurate evaluation of CMOS short-circuits power dissipation for short-channel devices," in Proc. Int. Symp. Low Power Electronics Devices, pp. 189--192, August 1996.

Digital Library

Google Scholar

[10]

J. M. Rabaey, Digital integrated circuits: a design perspective, Upper Saddle River, NJ: Prentice Hall, 1996.

Digital Library

Google Scholar

Cited By

View all

CAO ZHAN PLYU H(2024)Computer-Aided Design of Cross-Voltage-Domain Energy-Optimized Tapered BuffersIEICE Transactions on Electronics10.1587/transele.2023ECP5049E107.C:9(245-254)Online publication date: 1-Sep-2024
https://doi.org/10.1587/transele.2023ECP5049
Pinciroli RGribaudo MSerazzi G(2017)Modeling Multiclass Task-Based Applications on Heterogeneous Distributed EnvironmentsAnalytical and Stochastic Modelling Techniques and Applications10.1007/978-3-319-61428-1_12(166-180)Online publication date: 8-Jun-2017
https://doi.org/10.1007/978-3-319-61428-1_12
Gebrehiwot MAalto SLassila P(2016)Optimal energy-aware control policies for FIFO serversPerformance Evaluation10.1016/j.peva.2016.06.003103(41-59)Online publication date: Sep-2016
https://doi.org/10.1016/j.peva.2016.06.003
Show More Cited By

Index Terms

Buffer sizing for minimum energy-delay product by using an approximating polynomial
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

Recommendations

Impact of buffer sizing on energy efficiency and performance

Internet router buffers are commonly made very large with the aim of minimising losses and maximising link utilisation, supported by the ever‐decreasing cost of memory. However, large packet queues not only increase the energy consumption, but can also ...
Buffer Sizing Experiments at Facebook
BS '19: Proceedings of the 2019 Workshop on Buffer Sizing

In this paper, we present the results of several rounds of buffer sizing experiments at Facebook. We describe how we change buffer sizes in data center and backbone routers and study the impact of buffer sizes on several performance metrics, including ...
Video Quality Driven Buffer Sizing via Frame Drops
RTCSA '11: Proceedings of the 2011 IEEE17th International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 01

We study the impact of video frame drops in buffer constrained multiprocessor system-on-chip (MPSoC) platforms. Since on-chip buffer memory occupies a significant amount of silicon area, accurate buffer sizing has attracted a lot of research interest ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

April 2003

320 pages

ISBN:1581136773

DOI:10.1145/764808

General Chair:
Mircea Stan
University of Virginia
,
Program Chairs:
David Garrett
Bell Labs Research, Lucent Technologies
,
Kazuo Nakajima
University of Maryland

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 April 2003

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

GLSVLSI03

Sponsor:

GLSVLSI03: Great Lakes Symposium on VLSI 2003

April 28 - 29, 2003

D. C., Washington, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Upcoming Conference

GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
437
Total Downloads

Downloads (Last 12 months)9
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

CAO ZHAN PLYU H(2024)Computer-Aided Design of Cross-Voltage-Domain Energy-Optimized Tapered BuffersIEICE Transactions on Electronics10.1587/transele.2023ECP5049E107.C:9(245-254)Online publication date: 1-Sep-2024
https://doi.org/10.1587/transele.2023ECP5049
Pinciroli RGribaudo MSerazzi G(2017)Modeling Multiclass Task-Based Applications on Heterogeneous Distributed EnvironmentsAnalytical and Stochastic Modelling Techniques and Applications10.1007/978-3-319-61428-1_12(166-180)Online publication date: 8-Jun-2017
https://doi.org/10.1007/978-3-319-61428-1_12
Gebrehiwot MAalto SLassila P(2016)Optimal energy-aware control policies for FIFO serversPerformance Evaluation10.1016/j.peva.2016.06.003103(41-59)Online publication date: Sep-2016
https://doi.org/10.1016/j.peva.2016.06.003
Gebrehiwot MAalto SLassila P(2016)Energy-performance trade-off for processor sharing queues with setup delayOperations Research Letters10.1016/j.orl.2015.12.00444:1(101-106)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.orl.2015.12.004
Cerotti DGribaudo MPinciroli RSerazzi G(2016)Stochastic Analysis of Energy Consumption in Pool Depletion SystemsMeasurement, Modelling and Evaluation of Dependable Computer and Communication Systems10.1007/978-3-319-31559-1_4(25-39)Online publication date: 2016
https://doi.org/10.1007/978-3-319-31559-1_4
Gebrehiwot MAalto SLassila P(2014)Optimal sleep-state control of energy-aware M/G/1 queuesProceedings of the 8th International Conference on Performance Evaluation Methodologies and Tools10.4108/icst.Valuetools.2014.258149(82-89)Online publication date: 9-Dec-2014
https://dl.acm.org/doi/10.4108/icst.Valuetools.2014.258149
Abbaspour SAjami APedram MTuncer EGarrett DLach JZukowski C(2004)TFAProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.988958(19-24)Online publication date: 26-Apr-2004
https://dl.acm.org/doi/10.1145/988952.988958

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Impact of buffer sizing on energy efficiency and performance

Buffer Sizing Experiments at Facebook

Video Quality Driven Buffer Sizing via Frame Drops

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations