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A comparison of four two-dimensional gate matrix layout tools

Authors:

R. M. OwensAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 698 - 701

https://doi.org/10.1145/74382.74507

Published: 01 June 1989 Publication History

Abstract

A comparison of four layout tools is presented. The layout style is a two-dimensional gate matrix. The first layout tool discussed uses “standard” simulated annealing. Annealing on gate clusters instead of individual gates can be used to improve the layout results. Two different ways of determining good gate clusters for use in the annealing process are compared. The first way uses clusters derived from user specified gate hierarchies, while the second determines clusters based on gate connectivity. The fourth layout tool uses a decomposition scheme based on quadrisection. Layout results for a set of benchmark circuits are presented for each of the tools.

References

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Digital Library

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Owens, R.M. and M.J. Irwin, Clustering Based Simulated Annealing Sea-of-Transistor Layout Tools, CS- 88-09, PSU, also submitted to IEEE Trans on CAD.

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Cited By

Donald S. Gelosh (2006)Deriving Efficient Area and Delay Estimates by Modeling Layout Tools32nd Design Automation Conference10.1109/DAC.1995.249981(402-407)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.249981
Hwang TOwens RIrwin MWang K(2006)Logic synthesis for field-programmable gate arraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.31747113:10(1280-1287)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.317471
Hwang CHsieh YLin YHsu Y(2006)An efficient layout style for two-metal CMOS leaf cells and its automatic synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.21500312:3(410-424)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.215003
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Information

Published In

cover image ACM Conferences

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE-CS\TCDA: TC Design Automation
SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

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DAC89

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DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Donald S. Gelosh (2006)Deriving Efficient Area and Delay Estimates by Modeling Layout Tools32nd Design Automation Conference10.1109/DAC.1995.249981(402-407)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.249981
Hwang TOwens RIrwin MWang K(2006)Logic synthesis for field-programmable gate arraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.31747113:10(1280-1287)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.317471
Hwang CHsieh YLin YHsu Y(2006)An efficient layout style for two-metal CMOS leaf cells and its automatic synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.21500312:3(410-424)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.215003
Gelosh DSteliff D(2000)Modeling layout tools to derive forward estimates of area and delay at the RTL levelACM Transactions on Design Automation of Electronic Systems10.1145/348019.3481485:3(451-491)Online publication date: 1-Jul-2000
https://dl.acm.org/doi/10.1145/348019.348148
Gelosh DSetliff DPreas B(1995)Deriving efficient area and delay estimates by modeling layout toolsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217562(402-407)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217562
Govindan RLangston MRamachandramurthi S(1993)A Practical Approach to Layout OptimizationThe Sixth International Conference on VLSI Design10.1109/ICVD.1993.669683(222-225)Online publication date: 1993
https://doi.org/10.1109/ICVD.1993.669683
Prabhu UPrangrle BSchweikert D(1992)Superpipelined control and data path synthesisProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.149650(638-643)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.149650
Irwin MOwens R(1989)Design issues in digit serial signal processorsIEEE International Symposium on Circuits and Systems10.1109/ISCAS.1989.100385(441-444)Online publication date: 1989
https://doi.org/10.1109/ISCAS.1989.100385

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