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VVDS: a verification/diagnosis system for VHDL

Published: 01 June 1989 Publication History

Abstract

In this paper, an interactive verification and diagnosis system for VHDL [Vm88], VVDS, is presented. In VVDS, hybrid simulation, which simulates with both numerical and symbolic data, is implemented to achieve an effective compromise of the enormous quantity of input test data in the conventional simulation and the complexity of symbolic expression in the symbolic execution. To support efficient user interface in the verification and diagnosis process, both on-line programming of commands and micro-probing capability to passively and actively probe any level of design hierarchy are provided.

References

[1]
L. Augustin, B. Gennant, Y. Huh, D. Luckham, and A. Stanculescu, "Verification of VHDL Design Using VAL," Proc. 25th DAC, 1988. pp.48-53
[2]
M.R. Barbacci, "Instruction Set Processor Specification ({SPS): The Notation and Its Applications," IEEE Trans. Computers, Vol. C-30, No.i, Jan. 1981.
[3]
M.C. Browne, E. M. Clark, D. L. Dill, and B. Mishra, "Automatic Verification of Sequential Circuits Using Temporal Logic," IEEE Transactions on Computer, Vol. C-35, No. t2, Dec., 1986.
[4]
K. Clark, D. Cowell, "Programs, Machines, and Computation," McGraw-Hill Book Company (UK) Limited. 1976.
[5]
LA. Darringer, "The Application of Program Verification Techniques to Hardware Verification," Proc. 16th DAC, San Diego, pp. 375-381, 1979.
[6]
"Logic Databook," National Semiconductor Corporation, Santa Clara, California, 1981.
[7]
C. A. Mead and L. A. Conway, "Introduction to VLSI System," Addisoni-Wesley Publishing Company, 1980, Sec. 8.3.
[8]
J. D. Oakley, "Symbolic Execution of Formal Machine Descriptions", Ph.D Thesis, Carnegie-Mellon University, Apr, 1979.
[9]
H. C. Ou, W. S. Feng, H. T. Liaw, "Test Sequence Generator," Proc. of EDMS, Tainan, Taiwan, 1986, pp.84-89.
[10]
N.C.E. Srinivas and V.D. Agrawal, "Formal Verification of Digital Circuits Using Hybrid Simulation," Circuit and Device, January 1988.
[11]
S.A. Szygenda, E.W. Thompson, "Digital Logic Simulation In a Time-Based, Table-Driven Environment: Part 1. Design Verification," IEEE Computer, Mar. 1975, pp.24-36.
[12]
K. M. Tran, "Design and Implementation of a Mixed-Level Logic Simulator," M. S. Thesis, National Taiwan University, June, 1985.
[13]
"IEEE Standard VHDL Language Reference Manual," the IEEE Inc., 1988.
[14]
"VHDL Hierarchical Sirnulator Program Specification," Intermetrics, Inc., Oct., 1985.

Cited By

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  • (1990)Efficient automatic diagnosis of digital circuits1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers10.1109/ICCAD.1990.129954(464-467)Online publication date: 1990

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cover image ACM Conferences
DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference
June 1989
839 pages
ISBN:0897913108
DOI:10.1145/74382
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1989

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DAC89: The 26th ACM/IEEE-CS Design Automation Conference
June 25 - 28, 1989
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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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  • (1990)Efficient automatic diagnosis of digital circuits1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers10.1109/ICCAD.1990.129954(464-467)Online publication date: 1990

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