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Toward a dataflow/von Neumann hybrid architecture

Author:

R. A. IannucciAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 16, Issue 2

Pages 131 - 140

https://doi.org/10.1145/633625.52416

Published: 17 May 1988 Publication History

Abstract

Dataflow architectures offer the ability to trade program level parallelism in order to overcome machine level latency. Dataflow further offers a uniform synchronization paradigm, representing one end of a spectrum wherein the unit of scheduling is a single instruction. At the opposite extreme are the von Neumann architectures which schedule on a task, or process, basis.

This paper examines the spectrum by proposing a new architecture which is a hybrid of dataflow and von Neumann organizations. The analysis attempts to discover those features of the dataflow architecture, lacking in a von Neumann machine, which are essential for tolerating latency and synchronization costs. These features are captured in the concept of a parallel machine language which can be grafted on top of an otherwise traditional von Neumann base. In such an architecture, the units of scheduling, called scheduling quanta, are bound at compile time rather than at instruction set design time. The parallel machine language supports this notion via a large synchronization name space.

A prototypical architecture is described, and results of simulation studies are presented. A comparison is made between the MIT Tagged-Token Dataflow machine and the subject machine which presents a model for understanding the cost of synchronization in a parallel environment.

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Index Terms

Toward a dataflow/von Neumann hybrid architecture
1. Computer systems organization
  1. Architectures

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 16, Issue 2

Special Issue: Proceedings of the 15th annual international symposium on Computer Architecture

May 1988

431 pages

ISSN:0163-5964

DOI:10.1145/633625

Issue’s Table of Contents

ISCA '88: Proceedings of the 15th Annual International Symposium on Computer architecture
June 1988
461 pages
ISBN:0818608617
Chairman:
H. J. Siegel
Purdue Univ., West Lafayette, IN

Copyright © 1988 Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 May 1988

Published in SIGARCH Volume 16, Issue 2

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https://doi.org/10.3390/nano14020203
Mah DPark HCho W(2024)Enhancement of the Synaptic Performance of Phosphorus-Enriched, Electric Double-Layer, Thin-Film TransistorsElectronics10.3390/electronics1304073713:4(737)Online publication date: 11-Feb-2024
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Hasina DYadav KMukherjee D(2024)Compliance-Free and Forming-Free Digital and Analog Resistive Switching in a Perovskite-Based Artificial Synaptic Device: Mimicking Classical Pavlovian LearningACS Applied Electronic Materials10.1021/acsaelm.4c003616:5(3676-3687)Online publication date: 30-Apr-2024
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