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Price/performance comparison of C.mmp and the PDP-10

Author:

Samuel H. FullerAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 4, Issue 4

Pages 195 - 202

https://doi.org/10.1145/633617.803580

Published: 17 January 1976 Publication History

Abstract

The analysis in this paper shows a multiprocessor like C.mmp to have a factor of three to four cost/performance advantage over uniprocessor systems such as the PDP-10 when implementations using similar technologies are considered. This comparison is shown to be very sensitive to memory prices and considerable attention is given to normalizing memory costs between C.mmp and the PDP-10.

An important part of this analysis is a comparison of the PDP-10 architecture with the PDP-11 architecture (i.e. the architecture of the processors of C.mmp). When the limited address space of the PDP-11 is not a problem, we see that to a close approximation it takes the same number of PDP-11 instructions (average length 25 bits) as PDP-10 instructions (length 36 bits) to represent a program.

While the comparison in this paper explicitly considers multiprocessor degradation factors such as memory interference, it does not address the problem of writing software systems capable of taking full advantage of the multiprocessor structures. The comparisons in this paper are primarily ofcused on comparing the hardware structures of uniprocessors and multiprocessors. Work is now in progress at CMU that is attempting to evaluate the effectiveness of both individual multiprocessor structures application programs and multiprogrammed systems operating on C.mmp.

References

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Amdahl, G., Lecture in course on cache memories and computer architecture (EE 392C), Stanford Universi-Winter quarter, 1970.

[2]

Baskett, F. and A. J. Smith, "Interference in Multiprocessor Computer Systems with Interleaved Memory." To appear in Comm. ACM (1975).

Digital Library

[3]

Baskett, F., Figure 1.1 is a revision of an unpublished graph developed by Forest Baskett (1975).

[4]

Bell, C. G. and A. Newell, Computer Structures: Readings and Examples, McGraw-Hill, New York, 1971.

Digital Library

[5]

Bell, C. G. et al., C.mmp: The CMU Multiminiprocessor Computer: Requirements and Overview of the Initial Design, Department of Computer Science Technical Report, Carnegie-Mellon University, Pittsburgh, Pa. (1971).

[6]

Bhandarkar, D. P. and S. H. Fuller, A Survey of Techniques for Analyzing Memory Interference in MultiProcessor Systems, Carnegie-Mellon University Technical Report, Pittsburgh, Pa. (April, 1973).

[7]

Computer Review, GML Corporation, Lexington, Mass., 1974.

[8]

(DEC, 1975), PDP-11/05/10/35/40 Processor Handbook, Digital Equipment Corporation, Maynard, Mass. (1973).

[9]

(DEC, 1975), LSI-11 Microcomputer, Digital Equipment Corporation, Maynard, Mass. (1975).

[10]

Intel 3002 Control Processing Element; Shottky Bipolar LSI Microcomputer Set, Intel Corporation, 1974.

[11]

McLaughlin, R. A., "A Survey of 1974 dp Budgets," Datamation, February 1974, 52-56.

[12]

Newell, A., P. Freeman, D. McCracken, G. Robertson, "The Kernel Approach to Building Software Systems," CMU 1970-71 Computer Science Research Review.

[13]

Newell,A., and G. Robertson, Some Issues in Programming Multi-Mini-Processors, Department of Computer Science Technical Report, Carnegie-Mellon University, Pittsburgh, Pa., January 1975.

[14]

O'Loughlin,J. F., "Microprogramming a Fixed Architecture Machine," Infotech State of the Art Report 23, Infotech Limited, Maidenhead, England, 1975.

[15]

Stone, H. S. (ed.), Introduction to Computer Architecture, SRA, Chicago, Illinois, 1975.

[16]

Strecker, W. D., Analysis of the Instruction Execution Rate in Certain Computer Structures, Ph.D. Dissertation, Carnegie-Mellon University, Pittsburgh, Pa., 1970.

Digital Library

[17]

Wulf, W. A. and C. G. Bell, "C.mmp—A Multi-Mini-Processor," AFIPS Conference Proc., Vol. 41, Part II, FJCC 1972, 765-777.

[18]

Wulf et al., "The Hydra Operating System," submitted to the Fifth ACM SIGOPS Symposium on Operating System Principles (November 1975).

Digital Library

Cited By

Yan YZhang X(1999)Profit-Effective Parallel ComputingIEEE Concurrency10.1109/4434.7669677:2(65-69)Online publication date: 1-Apr-1999
https://dl.acm.org/doi/10.1109/4434.766967
Wood DHill M(1995)Cost-Effective Parallel ComputingComputer10.1109/2.34800228:2(69-72)Online publication date: 1-Feb-1995
https://dl.acm.org/doi/10.1109/2.348002
Shimor AWallach Y(1978)A Multibus-Oriented Parallel Processor SystemIEEE Transactions on Industrial Electronics and Control Instrumentation10.1109/TIECI.1978.351523IECI-25:2(137-141)Online publication date: May-1978
https://doi.org/10.1109/TIECI.1978.351523
Show More Cited By

Index Terms

Price/performance comparison of C.mmp and the PDP-10
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. General and reference
  1. Cross-computing tools and techniques
    1. Performance

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 4, Issue 4

January 1976

210 pages

ISSN:0163-5964

DOI:10.1145/633617

Issue’s Table of Contents

ISCA '76: Proceedings of the 3rd annual symposium on Computer architecture
January 1976
215 pages
ISBN:9781450374132
DOI:10.1145/800110
Chairmen:
Michael J. Flynn,
Oscar N. Garcia,
Daniel P. Siewiorek

Copyright © 1976 Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 January 1976

Published in SIGARCH Volume 4, Issue 4

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Cited By

Yan YZhang X(1999)Profit-Effective Parallel ComputingIEEE Concurrency10.1109/4434.7669677:2(65-69)Online publication date: 1-Apr-1999
https://dl.acm.org/doi/10.1109/4434.766967
Wood DHill M(1995)Cost-Effective Parallel ComputingComputer10.1109/2.34800228:2(69-72)Online publication date: 1-Feb-1995
https://dl.acm.org/doi/10.1109/2.348002
Shimor AWallach Y(1978)A Multibus-Oriented Parallel Processor SystemIEEE Transactions on Industrial Electronics and Control Instrumentation10.1109/TIECI.1978.351523IECI-25:2(137-141)Online publication date: May-1978
https://doi.org/10.1109/TIECI.1978.351523
Halsall FFenesan A(1978)Software aspects of a closely coupled multicomputer systemIEE Journal on Computers and Digital Techniques10.1049/ij-cdt.1978.00071:1(21)Online publication date: 1978
https://doi.org/10.1049/ij-cdt.1978.0007
(1978)BIBLIOGRAPHYComputer Engineering10.1016/B978-0-932376-00-8.50036-0(553-561)Online publication date: 1978
https://doi.org/10.1016/B978-0-932376-00-8.50036-0
Rajput SChen JHsu SGuimaraes M(2005)State based authenticationProceedings of the 43rd annual ACM Southeast Conference - Volume 210.1145/1167253.1167292(160-165)Online publication date: 18-Mar-2005
https://dl.acm.org/doi/10.1145/1167253.1167292
Yan YZhang X(1999)Profit-Effective Parallel ComputingIEEE Concurrency10.1109/4434.7669677:2(65-69)Online publication date: 1-Apr-1999
https://dl.acm.org/doi/10.1109/4434.766967
Wood DHill M(1995)Cost-Effective Parallel ComputingComputer10.1109/2.34800228:2(69-72)Online publication date: 1-Feb-1995
https://dl.acm.org/doi/10.1109/2.348002
Sauer CChandy K(1979)The impact of distributions and disciplines on multiple processor systemsCommunications of the ACM10.1145/359046.35905322:1(25-34)Online publication date: 1-Jan-1979
https://dl.acm.org/doi/10.1145/359046.359053
Stanley PMcCluskey EWakerly JCrockett EBredt TLu DvanCleemput WOwicki SOgus RApte RBeaurdy MLosq J(1978)Address size independence in a 16-bit minicomputerProceedings of the 5th annual symposium on Computer architecture10.1145/800094.803042(152-158)Online publication date: 3-Apr-1978
https://dl.acm.org/doi/10.1145/800094.803042
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