Article

An 8-b nRERL microprocessor for ultra-low-energy applications

Authors:

Seokkee Kim,

Jun-Ho Kwon,

Soo-Ik ChaeAuthors Info & Claims

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Pages 27 - 28

https://doi.org/10.1145/370155.370242

Published: 30 January 2001 Publication History

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Abstract

We describe the design of an nRERL microprocessor for ultra-low-energy applications. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit using only nMOS transistors, which can be operated at the leakage-current level [1]. We focus on two main issues; first, the design of a full adiabatic microprocessor, which uses only adiabatic components for all the functional blocks, second, the energy consumption of the nRERL microprocessor including its clocked power generator (CPG). With the experimental results, the nRERL microprocessor consumed 26.22 pJ at 440 kHz.

References

[1]

J. Lim, D. -G. Kim, and S. -I. Chae, "nMOS reversible energy recovery logic for ultra-low-energy applications," IEEE JSSC, pp. 865-875, Jun. 2000.

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[2]

C. J. Vieri, "Pendulu: a reversible computer architecture," M.S. thesis, Massachusetts Institute of Technology, June1995.

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[3]

W. C. Athas, N. Tzartzanis, L. "J." Svensson, L. Peterson, H. Li, X. Jiang, and W. -C. Liu, "AC-1: a clocked-powered microprocessor," in Proc. of ISLPED, Aug. 1997, pp. 328-333.

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[4]

J. -H. Kwon, J. Lim, and S. -I. Chae, "A Three-Port nRERL Register Rile for Ultra-Low-Energy Applications," in Proc. of ISLPED, Jul. 2000.

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[5]

J. Lim, D. -G. Kim, and S. -I. Chae, "Reversible energy recovery logic circuit and its 8-phase clocked power generator for ultra-low-power applications," IEICE Trans. on Electronics, vol. E82-C, no. 4, pp. 646-653, April 1999.

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Cited By

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Guan ZLi WDing WHang YNi L(2011)An Arithmetic Logic Unit design based on reversible logic gatesProceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing10.1109/PACRIM.2011.6033020(925-931)Online publication date: Aug-2011
https://doi.org/10.1109/PACRIM.2011.6033020
Kim SChae SRoy KTiwari V(2005)Complexity reduction in an nRERL microprocessorProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077649(180-185)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077649
Seokkee Kim Soo-lk Chae (2005)Complexity reduction in an nRERL microprocessorISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.10.1109/LPE.2005.195511(180-185)Online publication date: 2005
https://doi.org/10.1109/LPE.2005.195511

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An 8-b nRERL microprocessor for ultra-low-energy applications

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Published In

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

January 2001

662 pages

ISBN:0780366344

DOI:10.1145/370155

Chairman:
Satoshi Goto
NEC Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 January 2001

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ASP-DAC01: Asia and South Pacific Design Automation Conference 2001

Yokohama, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Guan ZLi WDing WHang YNi L(2011)An Arithmetic Logic Unit design based on reversible logic gatesProceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing10.1109/PACRIM.2011.6033020(925-931)Online publication date: Aug-2011
https://doi.org/10.1109/PACRIM.2011.6033020
Kim SChae SRoy KTiwari V(2005)Complexity reduction in an nRERL microprocessorProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077649(180-185)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077649
Seokkee Kim Soo-lk Chae (2005)Complexity reduction in an nRERL microprocessorISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.10.1109/LPE.2005.195511(180-185)Online publication date: 2005
https://doi.org/10.1109/LPE.2005.195511

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