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Sadram: A new Memory Addressing Paradigm

Published: 08 April 2024 Publication History

Abstract

The purpose of the Sadram Architecture (Self Addressing DRAM) is to minimize CPU memory traffic used merely for address computations. These savings are achieved by providing a symbolic addressing mode alongside the conventional linear mode. Linear addresses, such as 0,1,2,3,…etc. are dense, numeric, and inextricably bound to the structure of memory; symbolic addresses, such as ‘hi’, ‘bye’, or ‘gone’, are not linear, not dense, and closer to real world addressing. Sadram provides direct benefits to the user in addition to improving access efficiency

References

[1]
Donald E Knuth. 1998. The Art of Computer Programmng Volume 3,3. Addison-Wesley, Boston, MA.
[2]
Samuel K. Moore. 2021. Memory Chips that Compute will Accelerate AI. https://spectrum.ieee.org/processing-in-dram-accelerates-ai.
[3]
R.L. Sites. 1996. It’s the Memory Stupid". Microprocessor Report 10, 10 (Aug. 1996).
[4]
Doron Swade. 2001. The Cogwheel Brain. Abacus, London.

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MEMSYS '23: Proceedings of the International Symposium on Memory Systems
October 2023
231 pages
ISBN:9798400716447
DOI:10.1145/3631882
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 April 2024

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Author Tags

  1. Configuration of memory cells
  2. DRAM
  3. Memory rows in sorted order
  4. Parallel processing of a row buffer
  5. Pipeline data movement
  6. Sequencer-array
  7. Sequencer-cell
  8. Sequencer-group
  9. Symbolic memory addressing

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  • Short-paper
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  • Refereed limited

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MEMSYS '23
MEMSYS '23: The International Symposium on Memory Systems
October 2 - 5, 2023
VA, Alexandria, USA

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