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RAMPART: RowHammer Mitigation and Repair for Server Memory Systems

Authors:

Wendy Elsasser,

Michael R. Miller,

James TringaliAuthors Info & Claims

MEMSYS '23: Proceedings of the International Symposium on Memory Systems

Article No.: 4, Pages 1 - 15

https://doi.org/10.1145/3631882.3631886

Published: 08 April 2024 Publication History

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Abstract

RowHammer attacks are a growing security and reliability concern for DRAMs and computer systems as they can induce many bit errors that overwhelm error detection and correction capabilities. System-level solutions are needed as process technology and circuit improvements alone are unlikely to provide complete protection against RowHammer attacks in the future. This paper introduces RAMPART, a novel approach to mitigating RowHammer attacks and improving server memory system reliability by remapping addresses in each DRAM in a way that confines RowHammer bit flips to a single device for any victim row address. When RAMPART is paired with Single Device Data Correction (SDDC) and patrol scrub, error detection and correction methods in use today, the system can detect and correct bit flips from a successful attack, allowing the memory system to heal itself. RAMPART is compatible with DDR5’s RowHammer mitigation features, as well as a wide variety of algorithmic and probabilistic tracking methods. We also introduce BRC-VL, a variation of DDR5’s Bounded Refresh Configuration (BRC) that improves system performance by reducing mitigation overhead and show that it works well with probabilistic sampling methods to combat traditional and victim-focused mitigation attacks like Half-Double. The combination of RAMPART, SDDC, and scrubbing enables stronger RowHammer resistance by correcting bit flips from one successful attack. Uncorrectable errors are much less likely, requiring two successful attacks before the memory system is scrubbed.

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Cited By

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Nam HBaek SWi MKim MPark JSong CKim NAhn J(2024)DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00083(1097-1111)Online publication date: 29-Jun-2024
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RAMPART: RowHammer Mitigation and Repair for Server Memory Systems

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MEMSYS '23: Proceedings of the International Symposium on Memory Systems

October 2023

231 pages

ISBN:9798400716447

DOI:10.1145/3631882

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M PMutyam MTavva V(2024)Cache Line Pinning for Mitigating Row Hammer AttackProceedings of the 53rd International Conference on Parallel Processing10.1145/3673038.3673114(802-811)Online publication date: 12-Aug-2024
https://dl.acm.org/doi/10.1145/3673038.3673114
Hassan HOlgun AYağlıkçı ALuo HMutlu OZurich E(2024)Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00074(949-965)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00074
Nam HBaek SWi MKim MPark JSong CKim NAhn J(2024)DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00083(1097-1111)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00083
Olgun AOsseiran MYağlıkçı ATuğrul YLuo HRhyner SSalami BLuna JMutlu O(2024)Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN58291.2024.00022(75-89)Online publication date: 24-Jun-2024
https://doi.org/10.1109/DSN58291.2024.00022

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