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Delay-optimal wiring plan for the microprocessor of high performance computing machines

Published: 28 January 2000 Publication History
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References

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C.J.Alpert, A.Devgan and S.T.Quay, "Buffer Insertion for Noise and Delay Optimization", Proc. of 35 th DAC, pp.362-367, 1998.
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N.Ohkubo, T.Kawashimo, M.Suzuki, Y.Suzuki, J.Kikuchi, M.Tokoro, R.Yamagata, E.Kamada, T.Yamashita, T.Shimizu, T.Hashimoto and T.Isobe, "A Fault-Detecting 400MHz Floating-Point Unit for a Massively-Parallel Computer", ISSCC Digest of Technical Papers, vol.42, pp.368-369, 1999.
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cover image ACM Conferences
ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference
January 2000
691 pages
ISBN:0780359747
DOI:10.1145/368434
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 January 2000

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